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The True Story of the Blue Bomber Oasys = Kronos
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Jedi Simon
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PostPosted: Thu Oct 24, 2013 6:56 pm    Post subject: The True Story of the Blue Bomber Oasys = Kronos Reply with quote

The True Story of the Blue Bomber Oasys Open Architecture Workstation
by Jedi Simon

Kronos in reality is the true Blue Bomber Oasys prototype.

So, here we are.

This is the true story by Michael Lauer, that made the research, so I will just tell

you the basic facts.

I shall go back to 1994, if you have a few minutes i will clear out what this is all

about.

This page is a tribute to the KORG OASYS project — a truly revolutionary

synthesizer concept which due to a lot of sad coincidences never saw the light of

day (at least in the originally developed version.

I’m very well aware that there is a KORG OASYS since 2005).

THE BLUE BOMBER STORY THE BLUE BOMBER STORY THE BLUE

BOMBER STORY THE BLUE BOMBER STORY THE BLUE BOMBER

STORY
THE BLUE BOMBER STORY THE BLUE BOMBER STORY THE BLUE

BOMBER STORY THE BLUE BOMBER STORY THE BLUE BOMBER

STORY
THE BLUE BOMBER STORY THE BLUE BOMBER STORY THE BLUE

BOMBER STORY THE BLUE BOMBER STORY THE BLUE BOMBER

STORY

The “Blue Bomber” hardware prototype.

Korg OASYS Blue Bomber Prototype
A Summary of OASYS features — based on a KORG press release from 1994

Custom, high-performance Digital Signal Processor (DSP) system

High-performance custom DSPs, designed specifically for OASYS(R) deliver

an unprecedented amount of synthesis power and flexibility. This power and

flexibility frees synthesis algorithms from their

traditional hardware-based limitations, and makes open-architecture, software-

based synthesis possible.
Software-based synthesis

OASYS(R) creates its synthesis and effects in software, not in hardware. This

is the basic concept behind all of the OASYS(R) features.
Supports many different types of synthesis

OASYS(R) supports all available synthesis technologies, currently including

physical modeling, additive synthesis, FM, true analog simulations, stereo sample

playback, vector synthesis, and wave

sequencing. New synthesis techniques will be created in the future; sound

designers will be able to build algorithms which use these techniques, and

OASYS(R) will be able to play those sounds.
Advanced, polyphonic physical modeling

OASYS(R) includes advanced, polyphonic physical modeling synthesis

algorithms. Instead of relying on a single, generic “physical modeling” algorithm,

OASYS(R) makes it possible to use many different

algorithms, each designed for a specific acoustic or electro-mechanical instrument.
Disk loaded, RAM-based algorithms

Synthesis and effects algorithms are loaded from disk, so that as sound

designers create new algorithms, they can be distributed quickly and cost-

effectively. There is no fixed set of ROM algorithms; all

algorithms are stored in RAM. New algorithms don’t require upgrades to the

operating system, even if they use completely new synthesis techniques. Sounds

and effects load their own algorithms

automatically, for instant, transparent upgrades.
Uncompromised, fully professional sound

OASYS(R) is simply the most flexible synthesis platform ever developed.

Sound designers can custom-build completely different algorithms for each sound,

free from the constraints of preset architectures.

This unprecedented flexibility allows sound designers to choose-and create the

best possible method for making a particular sound, and fine-tune its timbre and

response to the player to degrees impossible on

any other instrument. 20-bit 48kHz, 128-times oversampling D/A converters on

all 8 outputs deliver the OASYS(R) sound with total clarity. Professional

musicians will appreciate the unparalleled quality of

OASYS(R)
Touch-screen and graphical interface

OASYS(R) features Korg’s new, intuitive TouchView(TM) graphical user

interface.

Expressive Controllers

In addition to its 76-key, after/ouch-sensitive keyboard, OASYS(R) provides

sophisticated controllers for unprecedented expressiveness, including a pressure-

sensitive ribbon controller, breath controller

input, modulation joystick with both normal and vector modes, and more.

The OASYS(R) system

The OASYS(R) system is a patented

(U.S. patent number 5,376,752),
( finally some interesting data )
I bet you did not know this information. So take a look and find out by yourself.

multiple digital signal processor (DSP) architecture, with the entire system clocking

in at over 900 million instructions per second. This incredible processing power

makes possible the revolutionary

breakthrough of OASYS(R) open architecture, software-based synthesis. Instead

of using dedicated hardware to produce oscillators, filters, and other synthesis

elements, OASYS(R) uses software to

construct them out of DSP resources. You can think of these DSP resources as

tiny building blocks, like the components which make up electronic circuits; put

together one way, they create an LFO; put

together another way, and they make an EQ an oscillator, a reverb, or an

envelope. Other instruments have been partially based on software technology, but

they’ve always been constrained by more or less

fixed architectures: a fixed number of voices of polyphony, limited amounts of

power for filters or other processing, predetermined basic signal paths, and most

importantly, a fixed number of synthesis

algorithms (usually, only one). This is where the OASYS(R) open architecture

comes in. OASYS(R) has no pre-defined oscillators, filters, envelopes, LFO’s, or

other synthesis elements; no fixed signal paths;

and no preset number of voices. Instead, each voice or effect uses DSP building

blocks to create all the elements that it needs, and then connects them together,

with complete freedom, to form an algorithm

(just like making patches on old-fashioned modular synthesizers-except that

OASYS(R) has a lot more blocks to work with). This means that each different

program or effect can have its own algorithm, if

necessary, specifically tailored to its needs. Since each voice can build its own

algorithm, OASYS(R) creates sound using any synthesis technology available,

including physical modeling, additive synthesis,

FM, analog simulations, stereo sample playback, vector synthesis, wave

sequencing, and more. Different synthesis techniques can be used alone or in

combination with each other; for instance, you can layer a

physically modeled guitar with FM bells and an analog pad. Synthesis and effects

algorithms are loaded into RAM from floppy disks or SCSI, just like program

data and samples; there is no fixed set of ROM

algorithms. New algorithms don’t require upgrades to the operating system, even

if they use completely new synthesis techniques. Instead, each program and effect

carries with it the algorithms that it requires,

so that OASYS(R) instantly, automatically upgrades itself every time a new sound

is loaded!

Software-based synthesis evolution follows revolution

The difference between traditional, fixed-architecture synthesizers and

OASYS(R) software-based synthesis is like the difference between a typewriter

and a computer. A typewriter can do only the one,

simple task that its hardware was designed to do: putting letters onto paper. A

computer, on the other hand, can simultaneously run word processing,

spreadsheet, graphics, and MIDI programs; and since

those functions rely primarily on software, and not on hardware, completely new

functionality can be added just by popping in a new disk. Similarly, OASYS(R)

comes out of the box with capabilities far

beyond those of a traditional synthesizer-but that’s just the beginning. Because its

synthesis is based on software, and not on hardware, OASYS(R) can grow along

with the state of the art. Since getting new

algorithms is as simple as loading a new disk of sounds-in fact, it happens almost

every time an OASYS(R) sound is loaded-OASYS(R) can and will feature new

types of synthesis as they are discovered.

OASYS(R) provides sound developers with the ultimate synthesis platform, for

which they can design new algorithms to the precise requirements of a particular

sound. Everyone knows that certain sounds are

best suited to their own synthesis methods (analog synth bass, for instance, or FM

electric pianos); whatever that best way of making the sound is, OASYS(R) will

use it. Because OASYS(R) allows this no-

compromise approach to sound development, Korg is able to provide musicians

with the ultimate in sonic performance.

OASYS(R) the state of the art In physical modeling

Due to the OASYS(R) Open Architecture Synthesis System and enormous

digital signal processing power, OASYS(R) is the world’s first polyphonic, multi-

timbral physical modeling synthesizer with

dynamic voice assignment. What is physical modeling synthesis? Physical modeling

is a new synthesis technique, which creates sound using complex mathematical

models of actual musical instruments. The

prime advantage of physical modeling is its greatly enhanced expressiveness,

especially when compared to sample playback. For instance, to capture the sound

of an instrument with samples, one records static

“snapshots” of the instrument played with different performance techniques-struck

softly or loudly, played with full or muted tone, etc. Expressiveness is limited to

switching or fading between these snapshots;

smooth transitions between different states, such as a single note starting softly and

building to overblowing, are difficult or impossible. With physical modeling, one

begins by building a model of the instrument’s

physical characteristics: whether it is a horn, a plucked string, a woodwind, a

bowed string, etc.; the size of the instrument, the material that its strings are made

of, the resonance of its soundboard, what sort of

reed it uses, the shape of its bore, and so on. This model can then be played in a

manner very similar to a real instrument, with smooth transitions in tone and

character controlled by the subtlest gestures of the

performer. When pitch bending on a guitar model, the bend resonates in the

guitar’s soundboard; when doing an octave rip on a trumpet, the pitch settles

naturally at the harmonics; when playing an electric

piano, the timbre continuously varies from a soft, bell-like tone with a light touch to

a hard, nasty growl when you dig into the keys. In addition to physical models of

acoustic musical instruments, OASYS(R)

features physical models of classic electronic and electro- mechanical musical

instruments, such as analog synthesizers, Hammond(TM) organs, and tine and

reed electric pianos. OASYS(R) analog synth

models set new standards for a digital synthesizer; its DSP power generates

incredibly punchy envelopes, oscillators with true pulse width modulation,

multimode resonant filters, and modulation routings at

audio rates. Last, but certainly not least, is perhaps the most exciting aspect of

physical modeling: the creation of instruments that do not-or cannot-exist in the

real world, and yet feel and play as if they were

natural, genuine, and musical. This area leaves OASYS(R) plenty of room to grow

into, and define, the future of synthesis.
TouchView(TM) Graphical User Interface

OASYS(R) uses Korg’s new TouchView(TM) graphical user interface system.

TouchView(TM) uses a large LCD and touch-screen to present the user with an

easy to use, intuitive graphical user interface.

Instead of pressing an endless series of cursor keys to select a parameter, for

instance, you just touch it on the screen. TouchView(TM) allows the user to easily

navigate the exceptionally flexible sound and

effects structures of OASYS(R) and allows easy upgrading as the OASYS(R)

system evolves.
Specifications

OASYS(R) Open Architecture Synthesis System, allowing a virtually unlimited

number of synthesis and effects algorithms. Supports physical modeling, additive

synthesis, FM, analog simulations, stereo

sample playback, vector synthesis, wave sequencing, and new technologies as

they are discovered. TouchView(TM) graphical user interface. Built-in 1.44 Mb

floppy disk and internal hard disk for storage of

the operating system, synthesis algorithms, effects and samples. Built-in SCSI port

for use with external hard drives, magneto-optical drives, and CD-ROM drives.

32 track multi-timbral with polyphonic

dynamic voice allocation. Up to 112 voices of polyphony or 112 simultaneous

effects (voices and effects share DSP resources; polyphony and number of effects

will vary depending on the algorithms used).

Up to 32 megabytes of sample RAM, using standard SIMMs. Custom-designed

database for managing files on disk and in memory. Extensive MIDI master

controller functions. 76 note keyboard with

velocity and aftertouch sensitivity. Pressure-sensitive ribbon controller, modulation

joystick (with normal and vector modes), an assignable slider, and 2 assignable

buttons. Breath controller input, 2 continuous

pedal inputs, 2 footswitch inputs. 24 bit internal processing. 20 bit, 128 times

oversampling D/A converters at a 48kHz sample rate. 8 polyphonic analog

outputs; balanced XLR main stereo outputs. 8 channel

ADAT(TM) compatible digital optical output. OASYS and TouchView(TM)

trademark of Korg Inc. and Korg U.S.A. ADAT(TM) a trademark of Alesis

corporation. Hammond(TM) a trademark Hamond

Suzuki Ltd.

A Comment from Dan Williams at Korg R&D — one of the OASYS(R) creators

Analog simulations is the closest match to emulations, so I’ll address that briefly.

In this context, simulations means that the OASYS can discretely model analog

synthesis methods, instead of merely running

a sampled waveform through a filter. This allows real-time control of oscillator

sync and pulse-width modulation, and audio-rate modulation (for incredibly

punchy envelopes and fast lfo’s). The Nord Lead and

the Korg Prophecy are other examples of dsp-based, analog-type synthesis.

Since the OASYS features the unique ability to load new algorithms from disk, it

will also be able to provide different envelope,

oscillator, and filter types (such as minimoog envelopes, or SEM filters).

Remember that the OASYS will have no fixed set of algorithms, for either

programs or effects. New algorithms are loaded every time that you load a sound.

OASYS supports synthesis methods and effects

algorithms by supporting over 70 atomic-level blocks, such as oscillators, filters,

delays, envelopes, mixers, math functions, and so on. As long as an algorithm can

be created by hooking those blocks together

(using our Macintosh-based algorithm development tool, SynthKit), the

OASYS will play it.

My personal disclaimer follows: Please note that the OASYS is *not* shipping

yet. That means that you have to take everything that I say with a grain of salt. It

also means that I’m *not* telling you to hold

your breath and save your pennies. As with computers, the ultimate synth is

always the *next* one, and you can’t make music with just a spec sheet in your

hands.
Dan.

1996/3: Time passes by

The KORG OASYS was first introduced at the winter NAMM 1994, then at the

Musikmesse Frankfurt 1995, several months later at the winter NAMM 1995 and

again at the Musikmesse Frankfurt 1996. I

heard that it is now scheduled to ship last quarter 1996, not for less than USD

10000. Well, let’s see…

Anyway, this architecture seems to be much more powerful than what the current

Yamaha VP-1 can offer for a price, approximately 3 times higher. (Nearby: The

Yamaha VP-1 shared the fate of the OASYS.

There was no successor but partial concepts were used in later models like the

AN1x and the FS1R).

And alla this infos date back to 1994 ...... ok?

1996/9: No OASYS

Several sources confirmed that Korg will NOT produce OASYS in its announced

form. In the meantime, Korg has released portions of the OASYS concept in

several products (Wavedrum, Prophecy,

Trinity) and there are rumours that the DSP and algorithm portion of OASYS will

be released as a software synthesizer PCI-card.
1995-1997: Byproducts

Korg has used part of the OASYS technologies in the mono synthesizer Prophecy

(for instance some oscillator models including resonant filters - the first time in a

KORG digital synthesizer since the analog

DW series)

Several OASYS features (not including the oscillator side, but at least some

resonant filters) were introduced with the Trinity Workstation … also known as

M1 Version 3.0. For instance, the new user

interface featuring the Touch Screen Display.On the german music fair 1997, Korg

showed a prototype of their upcoming virtual synthesizer Z1, which is supposed to

be released this year. It will include some

of the algorithms which debuted in OASYS, but won’t allow you to create new

algorithms.
1998: The Road goes on

Well, after all… the Z1 is shipping for quite a while now - but it does not really

fulfill the promises that the OASYS has made 1994. It seems that the time for the

OASYS concept has not come yet… be it due

to the lack of good algorithms or the lack of processing power.

In the meantime, two outstanding products are shipping, which come closer to the

OASYS synthesizer (albeit from different sides) than the current KORG

synthesizers. The first one is the Clavia Nord

Modular, the first virtual modular synthesizer. It is a great one. Be sure to check it

out.

The second one is created by Creamware, which debuted with the TripleDat HD

recording system. They have released the SCOPE audio card, which is a PCI

card with 14 AnalogDevices SHARC DSPs

and the PULSAR, a PCI card with 6 AnalogDevices SHARC DSPs. SCOPE

and PULSAR are modular DSP workstations. While the SCOPE environment

allows you to create complete new algorithm

parts (for instance, new filters or new oscillators), the PULSAR only allows you to

use these components in a modular way. But nevertheless, there’s a lot to play

with.

As far as I can see now, the purpose of this page has become a bit obsolete since

there is no sign of an OASYS concept successor manufactured by KORG.

Therefore, it is most likely that I won’t update this

page anymore. Maybe there will be a new page dealing with the components of

the studio of the future… we’ll see…

1999/2: Odysseus?

And just when you think a file is closed, there are new rumours floating around…

rumours that KORG will introduce a new synthesizer on the Frankfurt

Musikmesse 1999 in March. A successor to the

OASYS… that is… a synth which comes a bit nearer to the OASYS than all the

derivates before. I heard someone dropping the name “Odysseus”. Sounds

interesting, but — of course — no specs or

pictures, just speculations based on rumours by someone who has a friend who

heard something.
1999/3: No, Triton

KORG introduced the new TRITON on the Musikmesse 1999. An updated

Trinity V3 with better sampling capabilities. IMHO just another boring variation on

the subject workstation… ahh… I begin to hate

this term. While it was fun to play with these things (I was really happy when I

produced the first track with my M1… ages ago), nowadays, I don’t think there’s

a feasible alternative to working with computer

based sequencers.

1999/6: OASYS PCI Card

Did you read the 1996 part of this website ? It says: “Several sources confirmed

that Korg will NOT produce OASYS in its announced form. In the meantime,

Korg has released portions of the OASYS

concept in several products like the Wavedrum, the Prophecy, the Trinity, and

there are rumours that the DSP and algorithm portion of OASYS will be released

as a software synthesizer PCI-card.

Yes indeed, it seems that my “good informed” sources either were fortune-tellers

or insiders. Anyway, it has happened: On the Summer NAMM 1999 — five years

after the initial press release of the KORG

OASYS keyboard — three years after my insider-information about the PCI card

— KORG announced the OASYS PCI card, a PCI 2.1 compliant tone

generation card. Not that I’m excited though…
2004/3: Ten years after

It’s been five years since the last news on this page. The OASYS PCI card has

not been a success in the market. In the meantime, KORG released yet another

interesting byproduct of the OASYS concept

— the KORG KARMA.
2004/9: Psssst…

Suddenly, after all this quietness, the codename OASYS starts floating around

again… there is something in the pipeline!
2005: Congratulations, it’s a workstation

The KORG OASYS has been presented on NAMM 2005. Yes, it’s kind of cool.

No, it’s not what we were waiting for since 1994. The third product with the name

OASYS is a fully featured production

studio… and it runs Linux!

Take a look at the design of the "Blue bomber". What does it look like?
Is ti the Oasys you know or does it look like the Kronos?

I believe that it took them 17 years to make OASYS, and that they lost quite a lot

of money on the project, because Production of the OASYS was officially

discontinued in April 2009. Korg sold just

over 3000 units worldwide. The final software update was released on November

24, 2009, whilst tecnology was changing so rapidly, that they did not even

consider that fact because they were too involved

in their project.


So, that's why they are selling it now with another name.

I love the way Korgs sound, and I play them, compose, create and enjoy playing

them, but nothing has really changed in the past years, according to the patent on

which they are made.

I'm expecting something really new from Korg. This is what I am looking for, and

sinsce the crisis many smaller companies evolved so rapidly that it will be difficult

for Japan to run as fast as they do, if Korg

does not go OPEN AND AIR.

So that's why I believe that Kronos is in fact the Blue Bomber.

Take care.


Jedi Simon


Here I will copy on this posts and publish on my web site in the oasys page that I
an creating, what I wrote this week and posted here and there in the forum

answering to friends, so that you do not have to look for all the posts, since this

research is a valuable one, and explains quite clearly

what is inside this workstation, informations that in fact
were missing.

Here are the Oasys specs: THESE ARE QUITE SIMPLE TO FIND, AND

YOU MIGHT JUMP THEM IF YOU ALREADY KNOW THEM, own the

manuals
or do not bother. I will write them here just to compare them later on with some

other data.

And here the specs of an Oasys workstation that truly was ahead of time.
( The father of Kronos in fact )

Keyboard OASYS 88 88-key Real Weighted Hammer Action (RH2)


Tone Generator Internal PCM: HD-1 High Definition Synthesizer
EXi

Analog Modeling: AL-1 Analog Synthesizer
Tonewheel Organ Modeling: CX-3 Tonewheel Organ

Maximum Polyphony (*1*2)

HD-1: 172 voices (172 oscillators)
AL-1: 84 voices
CX-3: 172 voices

Number of Programs 1,664 user memory programs come preloaded
Number of Combinations 1,792 user memory combinations (384 come

preloaded)
Number of Drumkits 152 user memory drumkit (40 come preloaded)
General MIDI 256 GM Level2 preset programs+ 9 GM Level2 drum preset

programs
Preset PCM 314MB (1,505 multisamples, 1,376 drum samples)
Expansion PCM Libraries

313MB - EXs 1 ROM Expansion: 229 multisamples, 1,483 drum samples
503MB - EXs 2 Concert Grand Piano: 5 stereo multisamples

Capacity of PCM RAM (*3) 500MB
Wave 374 user memory, 150 preload

PCM Program Advanced Vector Synthesis Control oscillator volumes, synth

parameters, effect parameters via the Vector joystick and the tempo-synced

Vector Envelope
Structure

Single: OSC1
Double: OSC1 and OSC2
Double mode lets you layer two completely separate synth voices, each with their

own velocity-switched oscillator, dual filters, EGs, LFOs, etc.

Oscillators 4 velocity zones per oscillator, with switching, crossfades and layering.

Each zone can play mono or stereo Multisamples or Wave Sequences.
Filters

Two multi-mode filters per voice: low-pass, high-pass, band-pass and band-reject
Four-mode filter routings: single, serial, parallel and 24dB mode

Driver Per voice non-linear driver and low boost circuit
EQ Three bands, with sweepable mid
Modulation Three envelope generators, two LFOs per voice, common LFO, four

key tracking generators, AMS (Alternate Modulation Source); modulate a large

number of synthesis parameters via LFOs,

Envelopes, and real-time controllers. Two AMS Mixers - combine and process

AMS sources. Add, multiply, smooth, quantize, and more.
Drumkit Supports both stereo/ and mono drum samples, four-stage velocity

switch/crossfade

EXi Program Common Advanced Vector Synthesis Control oscillator volumes

and synthesis & effects parameters via the Vector Joystick and the tempo-

synchronized Vector Envelope.
Modulation Common Step Sequencer: 32-step sequencer with smoothing,

adjustable step duration, and tempo synchronization. AMS (Alternate Modulation

Source); modulate a large number of synthesis

parameters via LFOs, Envelopes, and real-time controllers, Common LFO, 2

Key Tracking Generators.
EQ Three bands, with sweepable mid

AL-1 Analog Synthesizer Oscillators New design ultra-low-aliasing oscillators

OSC1, OSC2, Sub-oscillator and noise generator; ring modulation, FM, and

Sync
Audio Input Run real-time audio through the synthesis engine, including ring mod,

filters, drive circuit, amp, and EQ
Filters

Two multi-mode filter (low-pass, high-pass, band-pass and band-reject) with four

types of filter routings (single, serial, parallel and 24dB mode)
MultiFilter mode (only Filter-A; modulateable mix of Low Pass, High Pass, Band

Pass, and dry input, for creating a wide variety of unique filter types and effects)

Driver Per-voice non-linear driver and low boost circuit
Modulation

Five Envelope generators, four per-voice LFOs, two Key Tracking generators,

and two AMS Mixers.Per-voice
Step Sequencer: 32-step sequencer with smoothing, adjustable step duration, and

tempo synchronization.


CX-3 Tonewheel Organ Tonewheel Organ Modeling A further evolution of Korg's

acclaimed CX-3. Phase-synchronous tonewheels (clean and vintage modes),

percussion, key click, wheel brake.
EX Mode Four additional, user-specified drawbars, and expanded percussion.
Internal Effects Rotary speaker, vibrato/chorus, amp modeling with overdrive, 3-

band EQ
Drawbar Controlled via nine front-panel sliders
Split Upper, Lower
Modulation Two AMS mixers

Combination Number of Timbres 16 Maximum
Master Keyboard Functionality Keyboard and velocity splits, layers, and

crossfades of up to 16 Programs and/or external MIDI devices
Advanced Vector Synthesis Control oscillator volumes and synthesis & effects

parameters via the Vector Joystick and the tempo-synchronized Vector Envelope.

Sampling System

Open Sampling System (resampling, In-Track sampling)
16bit/48kHz stereo/mono samping, maximum 512MB memory
4,000 samples/1,000 multisamples (128 indexes per multisample)
Direct sampling (ripping) from audio CD (CD-DA)
Able to load Korg format, AKAI S1000/S3000 data (with advanced Program

parameter conversion), AIFF, and WAVE formats
Time Stretch, Time Slice, Crossfade Loop, and other standard editing features


Effects Insert Effects 12 Insert Effects; in-line processing, stereo in / stereo out.
Master Effects Two Master Effects; two effects sends, stereo in / stereo out.
Total Effects Two Total Effects; for overall processing on the main outputs, such

as compression, limiting, and EQ; stereo in / stereo out.
Timber EQ High, low, and sweepable mid band. Per Program in Program Mode,

per Timbre in Combi mode (16 total), and per Track in Sequence mode (32

total).
Effect Types 185 types (Every type can be used as an insert, master or total

effect).
Dynamic Modulation Real-time control of effects parameters.
Common LFO Synchronized LFO modulation of multiple effects.
Effects Control Busses Two stereo side chains (for compressors, gates, vocoders,

etc.).
Record Busses Two stereo busses (for sampling and recording).

KARMA KARMA*** Modules One module in Program mode, four modules in

Combination and Sequencer modes; independent, programmable real-time control

settings for each Module.
Generated Effects (GE) 2,000 presets. New RTC (Real Time Controller) Models

provide more consistent control of KARMA parameters.
Controllers

ON/OFF, LATCH, CHORD, ASSIGN, MODULE, CONTROL, KARMA

REALTIME CONTROL SLIDERS [1] - [8], KARMA SCENE [1] - [8],

KARMA SWITCHES [1] - [8], KARMA Waveform

Control function, GE Sub-Category function, Auto RTC (Real Time Control)

setup function.
KARMA Waveform Control (change Multisamples via the KARMA engine), GE

Sub-Categories, Free Randomize function, Time Signature Control, Tempo

synchronization, Auto RTC (Real Time Control)

setup.


Sequencer
/HDR Tracks 16-track MIDI sequencer + 16-track hard disk recorder + master

track.
Number of Songs 200 songs
Resolution 1-192 ppq
Tempo 40.00 – 240.00 (1/100 BPM resolution)
Maximum Memory 400,000 MIDI events or 300,000 audio events
MIDI Tracks

16 tracks plus the master track
150 preset/100 user patterns (per song)
16 preset/16 user template songs
Format: Korg (OASYS) format, SMF formats 0 and 1

Audio Tracks 16-track playback, 4-track simultaneous recording WAV file format

Maximum single-file recording time (mono): 80 minutes Automation: Volume, Pan,

EQ, and Send1/2 5,000 regions (max.),

Event Anchors , BPM Adjust.
RPPR (Realtime Pattern Play & Record 1 Pattern set per song

Controllers Performance Controllers

Vector joystick
Korg Joystick
Ribbon controller
Switches 1 & 2

Pads 1-8 Velocity-sensitive drum pads and chord triggers

Control Surface CONTROL ASSIGN Switches Assigns the Control Surface to

TIMBRE/TRACK, AUDIO, EXTERNAL, R.TIME KNOBS/KARMA, or

TONE ADJUST.
MIXER KNOBS Switch Assigns the Mixer Knobs to either CHANNEL STRIP

or INDIVIDUAL PAN.
Knobs 1-8 (w/LED value indicators) 1-192 ppq
Switches 1-8 (Upper Row) Channel Strip, Individual Pan, External MIDI,

Realtime modulation, Tone Adjust.
Switches 1-8 (Lower Row) Select/Solo, External MIDI, KARMA Switches,

Tone Adjust
Master Slider Volume, External MIDI, Tone Adjust
KARMA Controller Section Switches = ON/OFF, LATCH, CHORD ASSIGN,

MODULE CONTROL

Disk Mode Load, save, utility, audio CD burning, audio CD playback, data filer

function (save/load MIDI System Exclusive data),CDs (UDF format read/write),

ISO9660 Level 1.

Display TouchView graphical user interface, 10.4 inch TFT, 640x480 dots,

adjustable angle.

Audio Connections (all are 24-bit) Outputs

Main Outputs (L/MONO, R): 1/4 Unbalanced; 1.1 k Stereo; 550 Mono

(L/MONO Only)
Individual 1-8: Max. output level: less than +18.5dBu (when load impedance is

100k)
Headphones: 1/4 stereo phone jack, output
S/PDIF: Optical, 24-bit, IEC60958, EIAJCP-1201, 48kHz or 96kHz
EXB-DI (optional ADAT** Output): ADAT format Output: 24-bit, 48kHz, 8-

Channel; BNC Word Clock In

Inputs 1 & 2 XLR-1/4 phone combi jacks (balanced), MIC/LINE switches, level

control knobs, phantom power switches
Inputs 3 & 4 1/4 phone jacks (unbalanced)
S/PDIF Optical, 24-bit

Other I/O Control

Damper pedal (half damper supported), assignable switch, assignable pedal
MIDI: In, Out, Thru
USB: Four high-speed USB 2.0 A connectors (for external USB devices)

Disk Drives Hard Drive 40GB HDD (2.5)
Optical CD-R/RW

Dimensions OASYS (76-key) 49.84 (W) x 19.06 (D) x 5.31
OASYS (88-key) 57.40 x 19.06 (D) x 5.31

Weight OASYS (76-key) 56.44 lbs
OASYS (88-key) 70.99 lbs

Crying or Very sad Embarassed Razz Mad Shocked Confused Cool Laughing Surprised Sad Smile Very Happy Wink Rolling Eyes Rolling Eyes Wink

Now let us compare them with Kronos.

KRONOS SPECS KRONOS SPECS KRONOS SPECS KRONOS SPECS

KRONOS SPECS KRONOS SPECS KRONOS SPECS
KRONOS SPECS KRONOS SPECS KRONOS SPECS KRONOS SPECS

KRONOS SPECS KRONOS SPECS KRONOS SPECS
KRONOS SPECS KRONOS SPECS KRONOS SPECS KRONOS SPECS

KRONOS SPECS KRONOS SPECS KRONOS SPECS

[System]

System: Kronos System Version 2.0

Keyboard:

88-key: RH3 (Real Weighted Hammer Action 3)
73-key: RH3 (Real Weighted Hammer Action 3)
61-key: Natural Touch Semi Weighted

[Tone Generator]

Synthesis Types: 9
SGX-1 Premium Piano (Acoustic Piano)
EP-1 MDS Electric Piano (Electric Piano)
HD-1 High Definition Synthesizer (PCM Virtual Memory Technology)
AL-1 Analog Synthesizer (Analog Modeling)
CX-3 Tonewheel Organ (Tonewheel Organ Modeling)
STR-1 Plucked String (Physical Modeling)
MOD-7 Waveshaping VPM Synthesizer (VPM Synthesis)
MS-20EX (CMT Analog Modeling)
PolysixEX (CMT Analog Modeling)
Maximum Polyphony*1*2:
SGX-1: 100 voices*3
EP-1: 104 voices
HD-1: 140 voices
AL-1: 80 voices
CX-3: 200 voices
STR-1: 40 voices
MOD-7: 52 voices
MS-20EX: 40 voices
PolysixEX: 180 voices

*A portion of the multicore processor in KRONOS is devoted to generating

voices, and a separate portion is devoted to generating effects. KRONOS

dynamically allocates the voice processing power

between the engines as necessary. The quoted maximum numbers of voices apply

when 100% of the voice processing power is devoted to a single engine.
*2 In rare cases, when a large number of processor-intensive effects are active

simultaneously (for instance, more than 14 O-Verbs), polyphony may be slightly

reduced.
*3 100 dual-stereo notes (It corresponds to 400 voices in the maximum.)

Number of Programs/Combinations/Drumkits:

2,560 user memory programs
(1,536 [768 HD-1+768 EXi] come preloaded)

1,792 user memory combinations
(480 come preloaded)

264 user memory drumkits
(78 come preloaded)

256 GM Level2 preset programs+ 9 GM Level2 drum preset programs

Preset PCM:

314 MB (ROM 1,505 multisamples, 1388 drum samples)

Build-in Expansion PCM Libraries:

EXs1 - ROM Expansion

EXs2 - Concert Grand Piano

EXs3 - Brass & Woodwinds

EXs4 - Vintage Keyboards

EXs5 - ROM Expansion 2

EXs6 - SGX-1 German D Piano

EXs7 - SGX-1 Japanese C Piano

EXs8 - Rock Ambience Drums

EXs9 – Jazz Ambience Drums

Capacity of PCM RAM:

Approx. 2 GB*4

*4 The memory available for RAM samples will change based on the use of

Expansion PCM libraries. About 1,129 MB is available when shipped from the

factory (when loading the file named

“PRELOAD.KSC”).

Wave Sequences:

598 user memory, 165

[SGX-1 Program]

Premium Piano:

PCM:

EXs6 - SGX-1 German D Piano

EXs7 - SGX-1 Japanese C Piano

EXs12 - SGX-1 Austrian Piano (Option Sound Libraries, DEMO Version is pre-

installed)

Piano Type:

32

Oscillator Control:

Damper Resonance, Damper Noise, Mechanical Noise, Note Release

[EP-1 Program]

MDS Electric Piano:

Tine and reed-type electric pianos powered by Multi-Dimensional Synthesis

(MDS), and vintage effects.

Electric Piano Model Types: 6

Tine EP I, Tine EP II, Tone EP V, Tine EP DMP, Reed EP200, Reed EP200A

Oscillator Control:

Harmonic Sound Level, Attack Noise, Level, Release Noise Level, Attack

Brightness, Hammer Width

Panel Control:

Tine Type: Preamp Volume, Tone (Treble, Bass), Vibrate (On/Off, Intensity,

Speed), Amp/Cabinet (On/Off, Drive)*5

Reed Type: Preamp Volume, Tone (Treble, Bass), Vibrate (Intensity, Speed),

Amp/Cabinet (On/Off, Drive)*5

*5 Each electric piano type has own amp/cabinet character.

Effect Types: 9

Small Phase, Orange Phase, Clack Phase, Vintage Chorus, Black Chorus, EP

Chorus, Vintage
Flanger, Red Comp, VOX Wah

[HD-1 Program]

Advanced Vector Synthesis:

Control oscillator volumes and synthesis & effects parameters via the Vector

Joystick and the tempo-synchronized Vector Envelope.

Structure:

Single: only OSC1, Double: OSC1 and OSC2.

Double mode lets you layer two completely separate synth voices, each with their

own velocity-switched oscillator, dual filter, EGs, LFOs, etc.

Two completely separate drumkits.

Oscillators:

8 velocity zones per oscillator, with switching, crossfades and layering

Each zone can play mono or stereo Multisamples or Wave Sequences

Filters:

Two multi-mode filters per voices (low-pass, high-pass, band-pass and band-

reject),

Four-mode filter routings (single, serial, parallel and 24dB mode)

Driver:

Per voice non-linear driver and low boost circuit

EQ:

Three bands, with sweepable mid

Modulation:

Three envelope generators, two LFOs per voice, common LFO, four key

tracking generators, AMS (Alternate Modulation Source), two AMS mixers

[EXi Program Common]

Advanced Vector Synthesis:

Control oscillator volumes and synthesis & effects parameters via the Vector

Joystick and the tempo-synchronized Vector Envelope.

Modulation:

Common Step Sequencer, AMS (Alternate Modulation Source), Common LFO,

2 Key Tracking Generators

EQ:

Three bands, with sweep-able mid

[AL-1 Program]

Oscillators:

Ultra-low-aliasing oscillators

OSC1, OSC2, Sub-oscillator and noise generator; ring modulation, FM and Sync

Audio Input:

Run real-time audio through the synthesis engine

Filters:

Two multi-mode filter (low-pass, high-pass, band-pass and band-reject) with four

types of filter
routings (single, serial, parallel and 24dB mode), MultiFilter mode (only Filter-A;

modulatable mix of Low Pass, High Pass, Band Pass, and dry input, for creating a

wide variety of unique filter types and

effects)

Driver:

Per-voice non-linear driver and low boost circuit

Modulation:

Five Envelope generators, four per-voice LFOs, two AMS Mixers;

Per-voice Step Sequencer.

[CX-3 Program]

Tonewheel Organ Modeling:

Phase-synchronous tonewheels (clean and vintage modes), percussion, key click,

wheel brake

EX Mode:

Four additional, user-specified drawbars, and expanded percussion.

Internal Effects:

Rotary speaker, vibrato/chorus, amp modeling with overdrive, 3-band EQ

Drawbar Control:

Controlled via nine front-panel sliders (via Tone Adjust)

Split:

Upper, Lower (even in EX mode)

Modulation:

Two AMS mixers

[STR-1 Program]

Physically Modeled String:
Includes physically modeled damping, decay, dispersion, nonlinearity, harmonics,

dual pickups, and more

String Excitation:
Three independent excitation sources can be used simultaneously: Pluck, Noise,

and PCM. 16 preset
“pluck” types, with modulatable width and randomization. Noise generator with

saturation and dedicated lowpass filter
PCM Oscillator:
Korg’s ultra-low-aliasing technology, as introduced in the HD-1; 4 velocity zones

per oscillator;
Uses any mono ROM, EXs, or RAM multisamples; PCM can either be used as

an excitation signal, or layered with the output of the string.
Excitation Filter:
Dedicated 2-pole multimode filter for shaping the string excitation; Filter can be

enabled/disabled separately for
each excitation source. Low Pass, High Pass, Band Pass, and Band Reject

modes

Audio Input and Feedback:
Run real-time audio through the string, including feedback through effects.

Modeled feedback includes modulate-able
instrument-to-amp distance and orientation.

Filters:
Dual multi-mode filters per voice; Single, Serial, Parallel (with split stereo output),

and 24dB (4-pole) configurations.
Low Pass, High Pass, and Band Reject modes

Multi Filter mode (Filter A only):
Modulatable mix of Low Pass, High Pass, Band Pass, and dry input, for creating

a wide variety of unique filter types and effects

Modulation:
5 Envelopes, 4 per-voice LFOs, 2 Key Track generators, String Tracking

generators, 4 AMS Mixers.


[MOD-7 Program]

Waveshaping VPM Synthesizer:

Combines Variable Phase Modulation (VPM), waveshaping ring modulation,

PCM sample playback, and subtractive synthesis; Able to convert-load SYX files.

Oscillators:

6 VPM/Waveshaper/Ring Modulation Oscillators:

Phase and modulatable pitch per oscillator; 101 Waveshaper tables plus

modulatable Drive and Offset; Use as oscillators, or as Waveshapers or Ring

Modulators for other signals.

PCM Oscillator:

Korg’s ultra-low-aliasing technology, as introduced in the HD-1. 4 velocity zones

per oscillator; Uses any mono ROM, EXs, or RAM multisamples; PCM can be

used as an FM modulator and/or layered with

the VPM Oscillators. Noise generator with saturation and dedicated low pass

filter.

Audio input:

Run real-time audio through the VPM Oscillators and filters.

Filters:

Dual multi-mode filters per voice. Parallel and 24 dB (4-Pole) configurations; Low

Pass, High Pass, Band Pass, and Band Reject modes

Multi Filter mode (Filter A only):

Modulatable mix of Low Pass, High Pass, Band Pass, and dry input, for creating

a wide variety of unique filter types and effects

Patch Panel:

Supports both algorithm (78 types) selection and free patching; Three 2-in, 1-out

mixers for scaling and merging audio, fully modulatable, with phase inversion.

Main 6-input stereo mixer, with modulatable pan

and volume, plus phase inversion

Modulation:

10 Envelopes, 4 per-voice LFOs, 9 Key Tracking generators, Per-voice Step

Sequencer, 4 standard AMS Mixers plus 4 simple AMS Mixers.

[MS-20EX Program]

Oscillators:

Ultra-low-aliasing oscillators; VCO1, VCO2, Ring Mod, Pink and White Noise

Generator

Audio Input:

Run real-time audio through the synthesis engine and ESP (External Signal

Processor)

Filters:

12dB/octave High Pass and Low Pass self-resonant filters

ESP section:
24dB/octave Low Cut and High Cut filters, available per voice.

Patch Panel:

Patchable audio and modulation, at audio rates

Patch Points:

Keyboard:
Keyboard CV Out, Keyboard Trigger Out, VCO1+VCO2 CV In, VCO2 CV In

VCO:
VCO1+VCO2 External Frequency Control In, VCO1 Out, VCO2 Out

VCF:
External Signal In, External HP Filter Cutoff Frequency Control In, External LP

Filter Cutoff Frequency Control In, HPF Out, LPF In, LPF Out

VCO+VCF:
Total External Modulation In

VCA:
External Initial Gain Control In, VCA In

EG:
EG1 Envelope Signal Normal Out, EG1 Envelope Signal Reverse Out, EG1+EG2

Trigger In, EG1 Trigger In, EG2 Envelope Signal Reverse Out

MG:
Triangle Out, Rectangle Out

Noise Generator:
Pink Noise Out, White Noise Out

Sample and Hold:
Clock Trigger In, Sample Signal In, S/H Out

Modulation VCA:
Control Voltage In, Signal In, Signal Out

Manual Controller:
Control Wheel Out, Momentary Switch

ESP:
Signal In, AMP Out, BPF In, BPF Out, F-V CV Out, Envelope Out, Trigger Out

Others:
EXi Audio In, Mixer 1 In, Mixer 1 Out, Mixer 2 In, Mixer 2 Out

ESP (External Signal Processor):

Use incoming audio as a trigger and/or CV source.

Modulation:

Original DAR and HADSR EGs 1 & 2, original MG (with MIDI sync), Sample-

and- Hold, MVCA; 4 additional multi-stage Envelopes, 4 additional per-voice

LFOs, and 4 AMS Mixers

[PolysixEX Program]

Oscillators:

VCO:
Saw, Pulse, PWM

Sub Oscillator:
Off, 1 octave below, 2 octaves below

Filter:

24dB/octave Low Pass self-resonant filter

Effects:

Integrated Polysix Chorus, Phase, and Ensemble



Arpeggiator:

Integrated MIDI-synced arpeggiator, with adjustable Range, Mode, and Latch

Modulation:

Original ADSR EG and MG (with MIDI sync), 2 additional multi-stage

Envelopes, 2 additional per-voice LFOs, and 4 AMS Mixers

[Combination]

Number of Timbres:

16 Maximum

Master Keyboard Functionality:

Keyboard and velocity splits, layers, and crossfades of up to 16 Programs and/or

external MIDI devices

Advanced Vector Synthesis:

Control oscillator volumes and synthesis & effects parameters via the Vector

Joystick and the tempo-synchronized Vector Envelope.

[Drumkit]

System:

Assignable stereo/mono samples with 8 velocity zones per oscillator (with

crossfade functions)

[Sampling]

System:

Open Sampling System (resampling, In-Track sampling)

Bit Depth/Sampling Frequency:

RAM: 16-bit/48 kHz stereo/mono sampling

DISK: 16 or 24-bit/48 kHz stereo/mono sampling

Sampling Time:

RAM: Depends on the amount of availale PCM RAM

DISK: Maximum 80 minutes stereo (879 MB: 16-Bit)

Sample Locations:

16,000 samples/4,000 multisamples (128 indexes per multisample)

Ripping:

Direct sampling (ripping) from audio CD (CD-DA)

Formats:

Korg format, AKAI S1000/S3000 data (with advanced Program parameter

conversion); SoundFont 2.0, AIFF, and WAVE formats

Editing:

Time Stretch, Time Slice, Crossfade Loop, and other standard editing features.

[Effects]

Insert Effects: 12

Stereo in / stereo out

Master Effects: 2

Stereo in / stereo out

Total Effects: 2

Stereo in / stereo out

Timbre EQ:

High, low, and mid band

Effect Types: 185

Modulation:

Dynamic Modulation and Common LFO

Effects Control Busses:

Two stereo side chains

Effect Presets: 783

Maximum 32 per 1 effect (Preset User)

[KARMA]


KARMA Modules:

One module in Program mode, four modules in Combination and Sequencer

modes

Generated Effects (GE):

2,048 presets, 1,536 Users (96 come Preload)

Controllers:

On/Off, Latch, Chord, Assign, Module, Control, KARMA Realtime Control

Sliders [1] – [8], KARMA Scene
[1] – [8], KARMA Switches [1] – [8], KARMA Wave-Sequencing, GE Sub

Category, Freeze Randomize, Time Signature Control, Tempo Synchronize, Auto

RTC (Real Time Control) setup

[Drum Track]

Drum Track Patterns:

697 preset (common with the preset patterns of the MIDI sequencer)

[Sequencer/HDR]

Tracks:

16-track MIDI sequencer + 16-track hard disk recorder + master track.

Number of Songs:

200 songs

Resolution:

1/480

Tempo:

40.00 – 300.00 (1/100 BPM resolution)

Maximum memory:

400,000 MIDI events
or 300,000 audio events

MIDI Tracks:

16 tracks plus the master track
697 preset/100 user patterns (per song)
18 preset/16 user template songs,

Format:

Korg (Kronos, OASYS) format, SMF formats 0 and 1.

Audio Tracks:

16-track playback, 4-track simultaneous recording, WAV file format 16bit/24bit.

Maximum single-file recording time (mono):

80 minutes

Automation:

Volume, Pan, EQ, and Send1/2; 5,000 regions (max.), Event Anchors, BPM

Adjust

RPPR (Realtime Pattern Play and Record):

1 Pattern set per song.

[General]

Disk Mode:

Load, save, utility, audio CD burning, audio CD playback, data filer function

(save/load MIDI System Exclusive data), CD-R/RW (UDF format read/write),

ISO9660 Level 1. *6

*6 Need to use with External USB CD Drive, etc.

Controllers:

Vector joystick, joystick, ribbon controller, switches 1 & 2

Control Surface:
Control Assign Switches:
Assigns the Control Surface to Timber/Track, Audio, External, Realtime

Knobs/KARMA, or Tone Adjust.

Mixer Knobs Switch:
Assigns the Mixer Knobs to either Channel Strip or Individual Pan, Reset Control

Switch, Solo Switch, Knobs 1-8, Switches 1-8 (Upper Row), Switches 1-8

(Lower Row), Sliders 1-8, Master Slider

KARMA Control:
On/Off, Latch, Chord Assign, module Control

Display:
TouchView graphical user interface, 8 inch TFT, SVGA (800x600 dots),

adjustable brightness

Outputs:
L/MONO, R:
1/4” Balanced; 350 ohms Stereo; 175 ohms Mono (L/MONO Only), Nominal

Level: +4.0 dBu, Maximum Level: +16.0 dBu (when load impedance is 600 ohms

or greater)

Individual 1-4:
1/4” Balanced; 350 ohms Stereo; 175 ohms Mono, Nominal Level: +4.0 dBu,

Maximum Level: +16.0 dBu (when load impedance is 600 ohms or greater)

Headphones:
1/4” stereo phone jack, output impedance: 33 ohms, Maximum Level: 60+60

mW (when load impedance is 33 ohms),

S/P DIF:
Optical, 24-bit, IEC60958, EIAJCP-1201, 48 kHz, (the same signals as

L/MONO, R)

USB-B:
24-bit, 48 kHz, 2 channels (the same signals as L/MONO, R)

Inputs:
Audio Inputs 1 and 2:

1/4” Balanced; Input Impedance: 10 kohms, Nominal Level: +4.0 dBu, Maximum

Level: +16 dBu,Source Impedance: 600 ohms, S/N: 95 dB (Typical), Dynamic

Range: 95 dB (Typical), Crosstalk: 95 dB (at

1 kHz, Typical)

S/P DIF:
Optical, 24-bit, IEC60958, EIAJCP-1201, 48 kHz

USB-B:
24-bit, 48 kHz, 2 channels

Control Inputs:
Damper pedal (half damper supported), assignable switch, assignable pedal

MIDI:
In, Out, Thru

USB:
USB A (TYPE A) x 2 (for connection to external USB devices)

USB B (TYPE B) x 1 (MIDI/audio interface, MIDI: 1(16ch) input / 1(16ch)

output, Audio: 2 channel input / 2 channel output)

2 USB high-speed ports (supports 480Mbps)

Principal Specifications:

Frequency Response:
20Hz-22kHz, +/-1.0 dB, 10k Ohms load

THD+N:
20Hz-22kHz, 0.01%, 10k Ohms load (typical)

S/N:
95 dB (typical)

Dynamic Range:
95 dB (typical)

Crosstalk:
95 dB, at 1 kHz (typical)

Disk Drives:
62 GB SSD (2.5”)

Power Consumption:
60 W

Dimensions: (W x D x H)

88-key: 57.28” x 16.18” x 5.71”
1,455 x 411 x 145 mm

73-key: 48.94” x 16.18” x 5.71”
1,243 x 411 x 145 mm

61-key: 41.42” x 14.25” x 5.28”
1,052 x 362 x 134 mm

Weight:
88-key: 50.71 lbs. / 23.0 kg

73-key: 44.75 lbs. / 20.3 kg

61-key: 27.56 lbs. / 12.5 kg

Accessories:
AC cord, Quick Start Guide, Accessory DVD Disc 1, 2 (DVDs include Kronos

Operation Guide, Parameter Guide, and Voice Name List PDF files; Video

Manual; KORG USB-MIDI Driver; System

Restore Data, etc.)




So this is the difference between the two different architectures.

One is an OPEN one, the other it said so, but never was, and concerning sounds

of course, you could put anything you want into a workstation of the third kind,

and it would play it up to it's maxium

possibilities. ( Don't ask me what a workstation of the third kind is, because I will

have to answer you.)

And this has nothing to do with progress and technology, but with courage, and

the wish to sell and give the opportunity to musicians and artists to reach the

highest levels possible in creativity or not.

The jo jo game, as I call it. Progressing in devolution.

Canon has been hacked. Hackon was the consequence.

I guess this is what is going to happen next. Hackorg. Simple as this.


Very Happy Smile Confused Cool Shocked Mad Razz Embarassed Crying or Very sad Rolling Eyes Surprised Sad Smile Very Happy Very Happy


Now guess what this is........

AND NOW GUESS WHAT THIS IS AND NOW GUESS WHAT THIS IS

AND NOW GUESS WHAT THIS IS AND NOW GUESS WHAT THIS IS
AND NOW GUESS WHAT THIS IS AND NOW GUESS WHAT THIS IS

AND NOW GUESS WHAT THIS IS AND NOW GUESS WHAT THIS IS
AND NOW GUESS WHAT THIS IS AND NOW GUESS WHAT THIS IS

AND NOW GUESS WHAT THIS IS AND NOW GUESS WHAT THIS IS

A full music studio to go, with 61-keys, external keyboard, 15" LCD touchscreen,

software, and more.

61-key semi-weighted synth action keyboard (World-class Fatar Technology)
Control Surfaces: Pitch Bend and Modulation Wheels, Trackpad with 2 Buttons,

External Keyboard ("QWERTY") Module, Assignable Alpha II Control Module

(5 Faders and 5 Modes Buttons, 3 Transpose

Buttons, 5 Direction Buttons and 5 Transport Buttons)
High Speed Dual-Layer 8.5GB/Disk CD and DVD Burner
Internal 15" color touchscreen LCD high-resolution (1024 x 768), external video

port for running dual monitors or a video projector

Included software
Open Labs RiFF virtual instrument host
Open Labs Karsyn V1.6 independent host for all of your PC-based Virtual

Instruments (VST)
4Front Technology Truepianos provides the real feeling of an acoustic piano
Wusik Wusikstation V3: powerful advanced hybrid vector & wave-sequencer

sampler virtual instrument
Lenna Digital Sylenth virtual analog synthesizer with over 700 presets
Reaper DAW with unlimited tracks that records audio-MIDI and integrates all of

your Karsyn presets in an easy-to-use, drag-and-drop format

Also included:
Ableton Live 7
GURU
Livid Cell
Acronus OEM
Chicken Systems Format Converter
Digital Sound Factory Proteus 2000
Digital Sound Factory MoPhat
Digital Sound Factory Virtuoso
Dimension LE
Mr Porter sounds

New V5 Sound Library Software:
Software: Microsoft Windows XP Home, Open Labs Custom GUI (Graphic User

Interface), Open Labs Karsyn V1.6, Open Labs Riff, Open Labs MimiK, PC

Angel

PREMIUM Factory Sound Library V5: Accordion, Addictive Drums, Artphase,

EVM Bassline, EVM Ultrasonique, BB303i, Blood Bucket, Crystal, Cubix,

Highlife, Lallapallooza Lite, MDA DX10, MDA

JX10, Microsynt, Mini Erhu, Minimal, Monolisa, Motion, Mr. Alias, Mr. Ray 22,

Mr. Ray 73, Mr. Tramp, Nanotron 2, Organized Trio, Phadiz, Plugsound Free,

Protoplasm 21, RealGuitar, Rez, Rogue, String

Synth, String Theory, STS-26, Super Spook Keys, Synth 1, Tiki Clav

Included Accessories:
Power cable
Quick Start guide
Allen wrench

Open Labs NeKo XXL Portable Keyboard Workstation
With a 15" touchscreen, 61 keys, integrated QWERTY keyboard, and optimized

Windows OS, NeKo XXL is an entirely new class of multimedia instrument. This

portable media production station was

specifically designed with keyboard playability, fusing both worlds of studio

engineering and live performance effortlessly.

The Open Labs NeKo XXL's optimized Windows OS natively supports virtually

any music application or plug-in developed for a PC. From Pro Tools to Nuendo,

Native Instruments Komplete to

Spectrasonics Omnisphere, NeKo LX5 does it all with ease.

This Gen5 NeKo XXL is equipped with the Bump MP integrated drum module,

designed to allow the user to create beats and trigger any sound, loop, or sample

in real time. Enhanced with a special Open

Labs version of Guru from FXpansion, key features of the Bump MP include: (16

plus 1) fully assignable pads, note repeat, max level, fixed level fader, transport

controls, chromatic mode, hold, pad tune,

multiple groove preset, and eight engines with 24 presets per engine.

This special keyboard workstation is also equipped with the Open Labs Mix/Edit

controller. The mixer section consists of multiple fully assignable controls including:

(Cool encoders, (Cool lighted buttons,

(Cool faders, (4 X 4) banks (total of 128 channels), and (1) master volume fader.

The edit section consists of multiple, fully assignable controls including: (Cool

encoders, (1) LCD display (for encoders), (4)

buttons, and (4) banks (total of 32 control parameters).

Exclusive to the Gen5 Open Labs NeKo XXL is the redesigned, fully mappable

Alpha II Panel, which allows the user to control any parameter they desire, and

two phantom-powered preamps in addition to

the eight I/Os. A full version of the multiple award-winning Ableton Live 7 is also

included for the first time in the XXL's history.

NeKo XXL is full of relevant and compelling sounds like Open Labs' The

Master's Series Library produced by multi-platinum producer Mr. Porter (Denaun

Porter), as well as Open Labs' own V5 sound,

sample, and loop library.

Part of the included software package, Open Labs Riff is an entirely new concept

in virtual instrument hosting. Written from the ground up by Open Labs, Riff

encompasses over 6 years of live performance

and studio production knowledge gathered from some of the world's top artists,

engineers, composers, and producers. Its advanced features include Live Controls

which allows the user to create any number

of virtual controls in real time that can be mapped to various effects and other

parameters. Advanced intelligence allows any number of virtual controllers to

manipulate any number of other virtual controllers,

providing automation for virtual instruments and effects. Rewire allows for this

powerful host application to be used within any DAW program.

Open Labs instruments are equipped with FireWire, USB, PCI EXPRESS and an

Ethernet port, allowing access to the Internet via a broadband connection. Open

Labs' tech support can log-in to your

system, and their online technicians can remotely view and diagnose any issue—

while you are still in your own studio.

Included in the NeKo XXL's arsenal is over 200 world-class virtual instruments

and effects, as well as over 20,000 presets with virtually unlimited capability for

third party plug-ins and applications.

Order today with the no-risk assurance of our Total Satisfaction and Low Price

Guarantees!

CPU: 2.5 GHz Core2Quad
Memory: 4GB RAM
Storage: 4TB
Expansion Slots: (1) 5.25" Dual-Layer DVD-RW burner (8.5GB/disc)
Audio I/O:
(1) High Performance Audio I/O Card with Low Latency including 24-bit/96kHz

professional 10-in/10-out: (2) mic/instrument preamp inputs (with Phantom Power

48V), (Cool analog line inputs, (10) analog

line outputs, S/PDIF digital I/O (coaxial), (1) Headphone Jack with Volume

Control
Connection: MIDI In/Out, 1) Sustain and (1) Expression ports, 2) USB 2.0 ports,

(1) FireWire 400 port, (1) Gigabit (10/100/1000) Ethernet port
Power Supply: 500+ Watt power supply, whisper quiet cooling fans (internal

chassis, processor & power supply)
Dimensions: 46"W X 20"D X 7"H
Weight: 46lb.


NOW COMPARE THE SPECS PLEASE
NOW COMPARE THE SPECS PLEASE
NOW COMPARE THE SPECS PLEASE
NOW COMPARE THE SPECS PLEASE

Thats why I wrote them up there for you.

This creature exists.

See what I mean when I say that Korg did not have the courage to go Open.

These are the simple facts. Data. No discussion about facts please.

30 giga vs 4 TB OH MY GOD
Compare anything you want, and you will see the difference.
It's not as nice, but OPEN LABS thought about creating something up to date.
Now, just tell me if the Korg workstations don't look obsolete compared to this

product.

The day KORG PRODUCERS will use UP TO DATE hardware it will be a

wonderful one.
even though I believe that they will ask too much for it....
I suppose that if they wanted to sell such a kind of workstation, they would ask

for something like 10.000 to 20.000 dollars.

Neko costs 6000 dollars, and it's worth 60.000 dollars plug ins.
Even if we are not talking avout the future, but about the past.
The apparently made this machine in 2006.


Got the picture?

It exists.

So, here we are.


THE TRUE STORY OF OASYS THE TRUE STORY OF OASYS THE TRUE

STORY OF OASYS THE TRUE STORY OF OASYS
THE TRUE STORY OF OASYS THE TRUE STORY OF OASYS THE TRUE

STORY OF OASYS THE TRUE STORY OF OASYS
THE TRUE STORY OF OASYS THE TRUE STORY OF OASYS THE TRUE

STORY OF OASYS THE TRUE STORY OF OASYS

This is the true story by Michael Lauer, that made the research, so I will just tell

you the basic facts.

I shall go back to 1994, and if you have a few minutes i will clear out what this is

all about.

This page is a tribute to the KORG OASYS project — a truly revolutionary

synthesizer concept which due to a lot of sad coincidences never saw the light of

day (at least in the originally developed version.

I’m very well aware that there is a KORG OASYS since 2005).

The “Blue Bomber” hardware prototype.

Korg OASYS Blue Bomber Prototype
A Summary of OASYS features — based on a KORG press release from 1994

Custom, high-performance Digital Signal Processor (DSP) system

High-performance custom DSPs, designed specifically for OASYS(R) deliver an

unprecedented amount of synthesis power and flexibility. This power and flexibility

frees synthesis algorithms from their

traditional hardware-based limitations, and makes open-architecture, software-

based synthesis possible.
Software-based synthesis

OASYS(R) creates its synthesis and effects in software, not in hardware. This is

the basic concept behind all of the OASYS(R) features.
Supports many different types of synthesis

OASYS(R) supports all available synthesis technologies, currently including

physical modeling, additive synthesis, FM, true analog simulations, stereo sample

playback, vector synthesis, and wave sequencing.

New synthesis techniques will be created in the future; sound designers will be

able to build algorithms which use these techniques, and OASYS(R) will be able

to play those sounds.
Advanced, polyphonic physical modeling

OASYS(R) includes advanced, polyphonic physical modeling synthesis

algorithms. Instead of relying on a single, generic “physical modeling” algorithm,

OASYS(R) makes it possible to use many different

algorithms, each designed for a specific acoustic or electro-mechanical instrument.
Disk loaded, RAM-based algorithms

Synthesis and effects algorithms are loaded from disk, so that as sound designers

create new algorithms, they can be distributed quickly and cost-effectively. There

is no fixed set of ROM algorithms; all

algorithms are stored in RAM. New algorithms don’t require upgrades to the

operating system, even if they use completely new synthesis techniques. Sounds

and effects load their own algorithms

automatically, for instant, transparent upgrades.
Uncompromised, fully professional sound

OASYS(R) is simply the most flexible synthesis platform ever developed. Sound

designers can custom-build completely different algorithms for each sound, free

from the constraints of preset architectures.

This unprecedented flexibility allows sound designers to choose-and create the

best possible method for making a particular sound, and fine-tune its timbre and

response to the player to degrees impossible on

any other instrument. 20-bit 48kHz, 128-times oversampling D/A converters on

all 8 outputs deliver the OASYS(R) sound with total clarity. Professional

musicians will appreciate the unparalleled quality of

OASYS(R)
Touch-screen and graphical interface

OASYS(R) features Korg’s new, intuitive TouchView(TM) graphical user

interface.

Expressive Controllers

In addition to its 76-key, after/ouch-sensitive keyboard, OASYS(R) provides

sophisticated controllers for unprecedented expressiveness, including a pressure-

sensitive ribbon controller, breath controller

input, modulation joystick with both normal and vector modes, and more.

The OASYS(R) system

The OASYS(R) system is a patented

(U.S. patent number 5,376,752), ( finally some interesting data )
I bet you did not know this information. So take a look and find out by yourself.

multiple digital signal processor (DSP) architecture, with the entire system clocking

in at over 900 million instructions per second. This incredible processing power

makes possible the revolutionary

breakthrough of OASYS(R) open architecture, software-based synthesis. Instead

of using dedicated hardware to produce oscillators, filters, and other synthesis

elements, OASYS(R) uses software to

construct them out of DSP resources. You can think of these DSP resources as

tiny building blocks, like the components which make up electronic circuits; put

together one way, they create an LFO; put

together another way, and they make an EQ an oscillator, a reverb, or an

envelope. Other instruments have been partially based on software technology, but

they’ve always been constrained by more or less

fixed architectures: a fixed number of voices of polyphony, limited amounts of

power for filters or other processing, predetermined basic signal paths, and most

importantly, a fixed number of synthesis

algorithms (usually, only one). This is where the OASYS(R) open architecture

comes in. OASYS(R) has no pre-defined oscillators, filters, envelopes, LFO’s, or

other synthesis elements; no fixed signal
Back to top
Jedi Simon
Guest





PostPosted: Thu Oct 24, 2013 7:10 pm    Post subject: The True Story of the Blue Bomber Oasys = Kronos II part Reply with quote

paths;

and no preset number of voices. Instead, each voice or effect uses DSP building

blocks to create all the elements that it needs, and then connects them together,

with complete freedom, to form an algorithm

(just like making patches on old-fashioned modular synthesizers-except that

OASYS(R) has a lot more blocks to work with). This means that each different

program or effect can have its own algorithm, if

necessary, specifically tailored to its needs. Since each voice can build its own

algorithm, OASYS(R) creates sound using any synthesis technology available,

including physical modeling, additive synthesis,

FM, analog simulations, stereo sample playback, vector synthesis, wave

sequencing, and more. Different synthesis techniques can be used alone or in

combination with each other; for instance, you can layer a

physically modeled guitar with FM bells and an analog pad. Synthesis and effects

algorithms are loaded into RAM from floppy disks or SCSI, just like program

data and samples; there is no fixed set of ROM

algorithms. New algorithms don’t require upgrades to the operating system, even

if they use completely new synthesis techniques. Instead, each program and effect

carries with it the algorithms that it requires,

so that OASYS(R) instantly, automatically upgrades itself every time a new sound

is loaded!

Software-based synthesis evolution follows revolution

The difference between traditional, fixed-architecture synthesizers and OASYS(R)

software-based synthesis is like the difference between a typewriter and a

computer. A typewriter can do only the one,

simple task that its hardware was designed to do: putting letters onto paper. A

computer, on the other hand, can simultaneously run word processing,

spreadsheet, graphics, and MIDI programs; and since

those functions rely primarily on software, and not on hardware, completely new

functionality can be added just by popping in a new disk. Similarly, OASYS(R)

comes out of the box with capabilities far

beyond those of a traditional synthesizer-but that’s just the beginning. Because its

synthesis is based on software, and not on hardware, OASYS(R) can grow along

with the state of the art. Since getting new

algorithms is as simple as loading a new disk of sounds-in fact, it happens almost

every time an OASYS(R) sound is loaded-OASYS(R) can and will feature new

types of synthesis as they are discovered.

OASYS(R) provides sound developers with the ultimate synthesis platform, for

which they can design new algorithms to the precise requirements of a particular

sound. Everyone knows that certain sounds are

best suited to their own synthesis methods (analog synth bass, for instance, or FM

electric pianos); whatever that best way of making the sound is, OASYS(R) will

use it. Because OASYS(R) allows this no-

compromise approach to sound development, Korg is able to provide musicians

with the ultimate in sonic performance.

OASYS(R) the state of the art In physical modeling

Due to the OASYS(R) Open Architecture Synthesis System and enormous digital

signal processing power, OASYS(R) is the world’s first polyphonic, multi-timbral

physical modeling synthesizer with dynamic

voice assignment. What is physical modeling synthesis? Physical modeling is a new

synthesis technique, which creates sound using complex mathematical models of

actual musical instruments. The prime

advantage of physical modeling is its greatly enhanced expressiveness, especially

when compared to sample playback. For instance, to capture the sound of an

instrument with samples, one records static

“snapshots” of the instrument played with different performance techniques-struck

softly or loudly, played with full or muted tone, etc. Expressiveness is limited to

switching or fading between these snapshots;

smooth transitions between different states, such as a single note starting softly and

building to overblowing, are difficult or impossible. With physical modeling, one

begins by building a model of the instrument’s

physical characteristics: whether it is a horn, a plucked string, a woodwind, a

bowed string, etc.; the size of the instrument, the material that its strings are made

of, the resonance of its soundboard, what sort of

reed it uses, the shape of its bore, and so on. This model can then be played in a

manner very similar to a real instrument, with smooth transitions in tone and

character controlled by the subtlest gestures of the

performer. When pitch bending on a guitar model, the bend resonates in the

guitar’s soundboard; when doing an octave rip on a trumpet, the pitch settles

naturally at the harmonics; when playing an electric

piano, the timbre continuously varies from a soft, bell-like tone with a light touch to

a hard, nasty growl when you dig into the keys. In addition to physical models of

acoustic musical instruments, OASYS(R)

features physical models of classic electronic and electro- mechanical musical

instruments, such as analog synthesizers, Hammond(TM) organs, and tine and

reed electric pianos. OASYS(R) analog synth

models set new standards for a digital synthesizer; its DSP power generates

incredibly punchy envelopes, oscillators with true pulse width modulation,

multimode resonant filters, and modulation routings at

audio rates. Last, but certainly not least, is perhaps the most exciting aspect of

physical modeling: the creation of instruments that do not-or cannot-exist in the

real world, and yet feel and play as if they were

natural, genuine, and musical. This area leaves OASYS(R) plenty of room to grow

into, and define, the future of synthesis.
TouchView(TM) Graphical User Interface

OASYS(R) uses Korg’s new TouchView(TM) graphical user interface system.

TouchView(TM) uses a large LCD and touch-screen to present the user with an

easy to use, intuitive graphical user interface.

Instead of pressing an endless series of cursor keys to select a parameter, for

instance, you just touch it on the screen. TouchView(TM) allows the user to easily

navigate the exceptionally flexible sound and

effects structures of OASYS(R) and allows easy upgrading as the OASYS(R)

system evolves.
Specifications

OASYS(R) Open Architecture Synthesis System, allowing a virtually unlimited

number of synthesis and effects algorithms. Supports physical modeling, additive

synthesis, FM, analog simulations, stereo sample

playback, vector synthesis, wave sequencing, and new technologies as they are

discovered. TouchView(TM) graphical user interface. Built-in 1.44 Mb floppy

disk and internal hard disk for storage of the

operating system, synthesis algorithms, effects and samples. Built-in SCSI port for

use with external hard drives, magneto-optical drives, and CD-ROM drives. 32

track multi-timbral with polyphonic dynamic

voice allocation. Up to 112 voices of polyphony or 112 simultaneous effects

(voices and effects share DSP resources; polyphony and number of effects will

vary depending on the algorithms used). Up to 32

megabytes of sample RAM, using standard SIMMs. Custom-designed database

for managing files on disk and in memory. Extensive MIDI master controller

functions. 76 note keyboard with velocity and

aftertouch sensitivity. Pressure-sensitive ribbon controller, modulation joystick

(with normal and vector modes), an assignable slider, and 2 assignable buttons.

Breath controller input, 2 continuous pedal inputs,

2 footswitch inputs. 24 bit internal processing. 20 bit, 128 times oversampling D/A

converters at a 48kHz sample rate. 8 polyphonic analog outputs; balanced XLR

main stereo outputs. 8 channel ADAT(TM)

compatible digital optical output. OASYS and TouchView(TM) trademark of

Korg Inc. and Korg U.S.A. ADAT(TM) a trademark of Alesis corporation.

Hammond(TM) a trademark Hamond Suzuki Ltd.

A Comment from Dan Williams at Korg R&D — one of the OASYS(R) creators

Analog simulations is the closest match to emulations, so I’ll address that briefly. In

this context, simulations means that the OASYS can discretely model analog

synthesis methods, instead of merely running a

sampled waveform through a filter. This allows real-time control of oscillator sync

and pulse-width modulation, and audio-rate modulation (for incredibly punchy

envelopes and fast lfo’s). The Nord Lead and

the Korg Prophecy are other examples of dsp-based, analog-type synthesis.

Since the OASYS features the unique ability to load new algorithms from disk, it

will also be able to provide different envelope,

oscillator, and filter types (such as minimoog envelopes, or SEM filters).

Remember that the OASYS will have no fixed set of algorithms, for either

programs or effects. New algorithms are loaded every time that you load a sound.

OASYS supports synthesis methods and effects

algorithms by supporting over 70 atomic-level blocks, such as oscillators, filters,

delays, envelopes, mixers, math functions, and so on. As long as an algorithm can

be created by hooking those blocks together

(using our Macintosh-based algorithm development tool, SynthKit), the OASYS

will play it.

My personal disclaimer follows: Please note that the OASYS is *not* shipping

yet. That means that you have to take everything that I say with a grain of salt. It

also means that I’m *not* telling you to hold

your breath and save your pennies. As with computers, the ultimate synth is

always the *next* one, and you can’t make music with just a spec sheet in your

hands.
Dan.

1996/3: Time passes by

The KORG OASYS was first introduced at the winter NAMM 1994, then at the

Musikmesse Frankfurt 1995, several months later at the winter NAMM 1995 and

again at the Musikmesse Frankfurt 1996. I

heard that it is now scheduled to ship last quarter 1996, not for less than USD

10000. Well, let’s see…

Anyway, this architecture seems to be much more powerful than what the current

Yamaha VP-1 can offer for a price, approximately 3 times higher. (Nearby: The

Yamaha VP-1 shared the fate of the OASYS.

There was no successor but partial concepts were used in later models like the

AN1x and the FS1R).

1996/9: No OASYS

Several sources confirmed that Korg will NOT produce OASYS in its announced

form. In the meantime, Korg has released portions of the OASYS concept in

several products (Wavedrum, Prophecy,

Trinity) and there are rumours that the DSP and algorithm portion of OASYS will

be released as a software synthesizer PCI-card.
1995-1997: Byproducts

Korg has used part of the OASYS technologies in the mono synthesizer Prophecy

(for instance some oscillator models including resonant filters - the first time in a

KORG digital synthesizer since the analog

DW series)

Several OASYS features (not including the oscillator side, but at least some

resonant filters) were introduced with the Trinity Workstation … also known as

M1 Version 3.0. For instance, the new user

interface featuring the Touch Screen Display.On the german music fair 1997, Korg

showed a prototype of their upcoming virtual synthesizer Z1, which is supposed to

be released this year. It will include some

of the algorithms which debuted in OASYS, but won’t allow you to create new

algorithms.
1998: The Road goes on

Well, after all… the Z1 is shipping for quite a while now - but it does not really

fulfill the promises that the OASYS has made 1994. It seems that the time for the

OASYS concept has not come yet… be it due

to the lack of good algorithms or the lack of processing power.

In the meantime, two outstanding products are shipping, which come closer to the

OASYS synthesizer (albeit from different sides) than the current KORG

synthesizers. The first one is the Clavia Nord

Modular, the first virtual modular synthesizer. It is a great one. Be sure to check it

out.

The second one is created by Creamware, which debuted with the TripleDat HD

recording system. They have released the SCOPE audio card, which is a PCI

card with 14 AnalogDevices SHARC DSPs

and the PULSAR, a PCI card with 6 AnalogDevices SHARC DSPs. SCOPE

and PULSAR are modular DSP workstations. While the SCOPE environment

allows you to create complete new algorithm

parts (for instance, new filters or new oscillators), the PULSAR only allows you to

use these components in a modular way. But nevertheless, there’s a lot to play

with.

As far as I can see now, the purpose of this page has become a bit obsolete since

there is no sign of an OASYS concept successor manufactured by KORG.

Therefore, it is most likely that I won’t update this

page anymore. Maybe there will be a new page dealing with the components of

the studio of the future… we’ll see…
1999/2: Odysseus?

And just when you think a file is closed, there are new rumours floating around…

rumours that KORG will introduce a new synthesizer on the Frankfurt

Musikmesse 1999 in March. A successor to the

OASYS… that is… a synth which comes a bit nearer to the OASYS than all the

derivates before. I heard someone dropping the name “Odysseus”. Sounds

interesting, but — of course — no specs or

pictures, just speculations based on rumours by someone who has a friend who

heard something.
1999/3: No, Triton

KORG introduced the new TRITON on the Musikmesse 1999. An updated

Trinity V3 with better sampling capabilities. IMHO just another boring variation on

the subject workstation… ahh… I begin to hate

this term. While it was fun to play with these things (I was really happy when I

produced the first track with my M1… ages ago), nowadays, I don’t think there’s

a feasible alternative to working with computer

based sequencers.
1999/6: OASYS PCI Card

Did you read the 1996 part of this website ? It says: “Several sources confirmed

that Korg will NOT produce OASYS in its announced form. In the meantime,

Korg has released portions of the OASYS

concept in several products like the Wavedrum, the Prophecy, the Trinity, and

there are rumours that the DSP and algorithm portion of OASYS will be released

as a software synthesizer PCI-card.

Yes indeed, it seems that my “good informed” sources either were fortune-tellers

or insiders. Anyway, it has happened: On the Summer NAMM 1999 — five years

after the initial press release of the KORG

OASYS keyboard — three years after my insider-information about the PCI card

— KORG announced the OASYS PCI card, a PCI 2.1 compliant tone

generation card. Not that I’m excited though…
2004/3: Ten years after

It’s been five years since the last news on this page. The OASYS PCI card has

not been a success in the market. In the meantime, KORG released yet another

interesting byproduct of the OASYS concept

— the KORG KARMA.
2004/9: Psssst…

Suddenly, after all this quietness, the codename OASYS starts floating around

again… there is something in the pipeline!
2005: Congratulations, it’s a workstation

The KORG OASYS has been presented on NAMM 2005. Yes, it’s kind of cool.

No, it’s not what we were waiting for since 1994. The third product with the name

OASYS is a fully featured production

studio… and it runs Linux!

Take a look at the design of the "Blue bomber". What does it look like?
Is ti the Oasys you know or does it look like the Kronos?

I believe that it took them 17 years to make OASYS, and that they lost quite a lot

of money on the project, because Production of the OASYS was officially

discontinued in April 2009. Korg sold just over

3000 units worldwide. The final software update was released on November 24,

2009, whilst tecnology was changing so rapidly, that they did not even consider

that fact because they were too involved in

their project.

So, that's why they are selling it now with another name.

I love the way Korgs sound, and I play them, compose, create and enjoy playing

them, but nothing has really changed in the past years, according to the patent on

which they are made.

I'm expecting something really new from Korg. This is what I am looking for, and

sinsce the crisis many smaller companies evolved so rapidly that it will be difficult

for Japan to run as fast as they do, if Korg

does not go OPEN AND AIR.

So that's why I believe that Kronos is in fact the Blue Bomber.

Take care.


Oh I was forgetting what's inside the box...... but please remember what Kronos

is....

Short Specs of a Kronos. You know that it is quite easy to play with

numbers.

Keyboard: 61‑key semi‑weighted; 73‑ and 88‑key piano‑weighted.
HD1 Synth Engine 314MB ROM, 1505 multisamples, 1388 drum samples.
Expansion Libraries EXs1 ROM expansion; EXs2 Concert Grand Piano; EXs3

Brass & Woodwinds; EXs4 Vintage Keyboards; EXs5 ROM Expansion 2; EXs6

SGX1 German D Piano; EXs7 SGX1

Japanese C Piano; EXs8 Rock Ambience Drums; EXs9 Jazz Ambience Drums.
Wave Sequences 165 preset, 374 user.
Expansion Instruments: SGX1 acoustic pianos, EP1 electro‑mechanical pianos,

AL1 virtual analogue synthesizer, MOD7 FM synthesizer, STR1 plucked string

synthesizer, MS20EX virtual analogue

synthesizer, PolysixEX virtual analogue synthesizer, CX3 virtual tonewheel organ.
Internal RAM 2GB.
Available Sample RAM 148MB after factory libraries loaded.
Internal Drive 30GB SSD.
Memory 1664 Programs, 1792 Combis, 152 Drum kits, 256 GM2 Programs and

nine GM2 drum kits.
Set Lists 128 lists, 128 slots per list.
Sampling 48kHz, 16-/24‑bit, 4000 samples, 1000 multisamples maximum
Effects Insert Effects: 12; Master Effects: two; Total Effects: two. 185 different

types with side‑chaining; 783 presets, maximum 32 presets per type. EQs: one

per track.
KARMA 2048 preset Generated Effects (GEs), 1536 User GEs, one module in

Program mode, four modules in Combi and Sequencer modes.
Drum Tracks 697 preset patterns, 1000 user patterns.
Sequencer/Recorder 16‑track MIDI sequencer, 16‑track hard disk recorder,

master track. Four‑track simultaneous recording, maximum 200 songs, 300,000

audio events, 400,000 MIDI events. Resolution:

480ppqn. Real-time Pattern Play and Record (RPPR): 1 Pattern set per song.
Screen TouchView, eight-inch TFT, 800x600 pixels.
Analogue Outputs Main L/R, four individual, headphones.
Analogue Inputs Two quarter‑inch TRS balanced jacks.
Optical S/PDIF In & Out, 24‑bit, 48kHz.
Control Inputs Damper, assignable switch, assignable pedal.
MIDI (DIN) In, Out, Thru.
USB A Two connections to external USB devices.
USB B MIDI & two‑channel audio interface, 24‑bit, 48kHz.

Why does it look so Obsolete, now that we met Neko?


Very Happy Shocked Confused Smile Sad Cool Laughing Surprised Crying or Very sad Razz Mad Embarassed Crying or Very sad

Wink Rolling Eyes Twisted Evil Razz Embarassed Cool Confused Smile Sad Surprised Laughing


OASYS MkII is KRONOS
OASYS MkII is KRONOS
OASYS MkII is KRONOS
OASYS MkII is KRONOS

OASYS — RIP?

Korg appear to have been careful to avoid calling the Kronos the OASYS MkII,

which would have been just as appropriate. I suspect that there is a commercial

reason for this. If they had done so, it would

have been reasonable for OASYS owners to expect some or all of the Kronos’s

new libraries and facilities to be made available as upgrades. By divorcing one

from the other, the company are, in effect,

saying, “How can we put Kronos inside OASYS? They are different products.”

Have you noticed that Kronos shape is in fact the true OASYS prototype that

they presented long ago?

This says it all.

They tried to create this monster but it was to early, and it costed them a lot of

money to build it.

Now that they are not wishing to spend too much, and are trying to get back all

the money they spent on that project, we meet Kronos.

I believe that it should not be intended as a new and different project, but as a part

of the first one.

Incompatibilities have beeen created in the two softwares, OS 1.3.3 AND

KRONOS 2.0 so that the Oasys owners will have to buy a new keyboard,

instead of upgrading Oasys to Kronos level.

Commercial decisions, of course.

Oasys Pcgs can be red by Kronos, but not the contrary.

My Idea was to create a Revolving doors program, so that the community, could

use them without any limitation, when suddenly
a question that I found in the post caught my attention, and so I found the answers

for you.

IF YOU WANT TO KNOW WHAT IS GOING TO COME NEXT,
then keep on reading.

I do not believe that Korg, Roland or Yamaha will jump ahead, and create

something really new. No mostrers anymore.

Neko by Open Labs did it, and without creating any fuss...

It's the agreement multinational have signed according to technological progress,

that runs the system.

So you have to take a look at softwares and virtual machines, to find out what is

really going to change things.

Hardware makers have been surpassed by programmers.

Home made hardware could be cheaper and more valuable, functional and

futuristic than any keyboard produced at the moment by the main companies.

I could build you one with spear parts in a couple of weeks.

Look at NEKO. If I love Korg sounds, I could simply colone a Kronos INTO IT

AND go VST plug ins.

It is as simple as this. Future does not belong to them any more, because they

made a fault when they said that OASYS was an open architecture, whilst it was

not. We all know what an OPEN SOURCE IS,

and programmers nowadays are able to answer directly to questions, tasks and

ideas that their friends ask them to put in practice.

When we all discovered tht inside the Oasys ther was a pentium 4, a

motherboard, and a pc put to pieces in an orizontal case, we realized that they did

exactly what we are doing today.

Software, is the key. Fast cpus, memory banks, and a perfect soundcard.

You might create your own keyboard with a powerful pc, 16 gig meme, touch

screen, etc... add a mixer, a 24 tracks recorder, 64 pads, or even a double touch

screen, 10 points, and there you are.
Software is most of the time free if you consider plugins.

You could go open source linux, so that no one could create copyright problems

to you, no slowing down dlls open all the time, and spyware, trojans, etc... ( you

know, industry uses open source all the time,

immediately, as soon as their product works fine with it - Android OS ).


It is only a matter of building the structure of the new keyboard, starting from

valuable pieces, that you could unite altogether in a 25 kg configuration that would

be cheaper that any keyboard you find around

today ). Build one yourself.

Software is around. It's up to you. Dinosours are for lazy people, not musicians.

Ready made stuff, where you anly have to buy sounds and cards, is something that

belonges to the past.

The spoilt it, because they wanted to run indefinitly the slowing down of progress

and technology to keep selling new models every two months.

Has anything really changed since Oasys? No.

But if you don't know what a Neko is, i shall explain this to you.

Take a look, and then, make up your mind.
The idea Korg had was a good one. This is the avrege person realization of that

concept, at half of the price, and if you make it by yourself, you would not spend

more than 2000 dollars.

These are the specs:

Another Neko creature.

A Timbaland-inspired, all-in-one music production station.

The Timbaland Special Edition NeKo (NeKo TSE) is an all-in-one production

studio powered by Windows XP, capable of running virtually any Windows XP

compatible software, including a variety of DAW

software, virtual instruments (VSTi), virtual effects (VST), and other music

applications.
Timbaland, one of the hottest producers in the past decade, wanted the ability to

work on his music from home on a larger unit and still be able to travel easily with

his other Open Labs creation, the MiKo. So

Open Labs obliged with the NeKo, which utilizes the same gear with matching

specs and software. It provides the features that most people are looking for, at a

more affordable price.

These Gen4 models are equipped with Intel Core2Quad processors providing

exceptional processing power. With the edition of Translator, specially written for

Open Labs by Chicken Systems, users can

easily convert and manage many different file types within the Open Labs

environment. Also included in the preinstalled software is Reaper from Cockos, a

DAW with unlimited tracks, which records audio-

midi and integrates all of the user's Karsyn presets in an easy-to-use, drag-and-

drop format.

The NeKo TSE features E-MU's new Proteus X2 Streaming Sound Module

V2.5 with over 10,148 instruments, including the new Ensoniq Urban Legends

Sound Library that contains the sounds from

Ensoniq's ASR/EPS/MR/ASR-X/ZR instruments. These sounds were specifically

requested by Timbaland, and are only available in the TSE units. Running in the

Proteus environment, these keyboards are

reborn, giving you an incredible combination of high-end audio quality with virtual

instruments that would cost you over $60,000 were you to buy the actual models

individually.

Included in this special edition is the Open Labs sound library V4, which contains

over 35-gigabytes of premium sounds, constituting 28,074 presets and Open

Labs Special Edition plugins, optimized by the

software developers for use with the NeKo.

Some of the other features include a 61-key semi-weighted synth action

keyboard, pitch bend and modulation wheels, a trackpad with 2 buttons, a full

(QWERTY) keyboard module, assignable alpha control

module, DJ Module, an internal 15" color touch screen LCD with high resolution,

and a built-in Presonus FireBox audio interface.

Presonus FireBox

The PreSonus FireBox is a 24-bit/96kHz FireWire Recording System with a 6-in,

10-out computer recording interface. It boasts 2 crystal-clear Class A preamps

with 45dB gain, ultra-wide 10Hz-50kHz

frequency response, and professional 24-bit/96kHz converters with 110dB

dynamic range for a big, musical sound.

It has 2 mic/instrument preamps with 48V phantom power conveniently located

on the front panel. It gives you 2 balanced TRS line inputs, 6 balanced TRS

analog outs, as well as MIDI and S/PDIF I/O. You

can record through 6 inputs and playback through 8 outputs simultaneously. It also

has a stereo headphone output and the main volume control on the front panel.

The FireBox is compatible with both Windows XP and Mac OS X and is

compatible with many popular ASIO/WDM and Core Audio based applications

including Sonar, Cubase, Nuendo, Logic, Digital

Performer, Premier, and many others.
Features

61-key semi-weighted synth action keyboard (with world-class Fatar Technology)
Built-in Presonus FireBox interface

Control Surfaces:

Pitch Bend and modulation wheels
Trackpad with 2 buttons
Keyboard ("QWERTY") module
Assignable alpha control module (5 faders, 5 modes buttons, 3 transpose buttons,

5 directions buttons, and 5 transport buttons)
DJ Module: Penny and Giles crossfader, 7 knobs, and 12 buttons

Audio I/O:

High performance audio I/O card with low latency including 24-bit/96kHz

professional 4-in/6-out
2 mic/instrument preamp inputs with Phantom Power of 48V
2 analog line inputs
6 analog line outputs
S/PDIF digital I/O (coaxial)
1 headphone jack with volume control

Display:

Internal 15" color touch screen LCD high resolution (1024 x 768)
External video port for running dual monitors or a video projector

Presonus FIreBox

24-bit/96kHz FireWire recording interface
2 front panel inputs with preamps and 48V phantom power
2 balanced TRS line inputs
6 balanced TRS analog outs
MIDI I/O
S/PDIF I/O
Recording and playback through 6 inputs and 8 outputs simultaneously
Stereo headphone output
Volume control
Compatible with most ASIO/WDM and Core Audio based applications

Connections:

MIDI In/Out
Sustain and Expression ports
2 USB 2.0 ports
FireWire 400 port
Gigabit (10/100/1000) Ethernet port

Software:

Microsoft Windows XP Home; Open Labs' Custom GUI, mFusion, Karsyn,

MimiK; E-MU Proteus X2 Streaming Sound Module V2.5; ChickenSys

Translator, Reaper

PREMIUM Factory Sound Library V4:

28,074 presets (over 35GB of sounds) from over 60 virtual instruments including:

E-MU's Ensoniq Urban Legends, Mo'Phatt X, Modern Symphonic Orchestra,

Old World Instruments, Vintage X Pro

Collection, Virtuoso X, and X2 Production Library, Truepianos, WusikStation V4,

Extra Wusik Sound Libraries (Wusik Sound Magazine 1-13, HQ Strings, Choirs,

GM), Purity, Sylenth 1, VB3 OL SE, Mr.

Ray22, Mr. Ray73, Mr. Tramp, Organized Trio V3, Realguitar V2.1 OL SE,

Discovery V2.10 OL SE, Vertigo V2.6 OL SE, HighLife V1.4, WIVI Trial Edt.,

Suburban Guitarist, Lollapalooza Lite OL SE,

BB303i V2, Synth 1, Addictive Drums Demo, Ticky Clav, Delay Lama, Crystal

V2.4, Sun RA, String Theory V1.5, Texture V1.2, Rez V2, Motion V2.8,

Plugsound Free, Mini Dizi, Mini Erhu, EPiano

Module, Rhodes Module, Bass Module, Rock, Bass Line, UltraSonique V1.1,

Syncoder 32-2, Spook Keys, Super Spook Keys, Cubix V1.0.1, Minimal V1.5,

Optik V1.4, Pandemonium V2, X-Fortuna,

Lazer Blade Free, Protoplasm 21 Free, STS-25 Free, Ph0ne, Rogue, MicroSynt,

Artphase V1.5, Mr. Alias V1.02, Blood Bucket V1, Monolisa V1.12, String

Synth, PhadiZ, and Accordion.

Included Accessories:

AC cord
Start guide
Owner's manual (PDF)
Motherboard manual
Open Labs Sounds Utilities and Drivers DVD
3 Reference Maps
2.5mm wrench
Additional screws and washers for hard drive upgrade


NOW I GUESS YOU UNDERSTAND WHAT I AM TALKING ABOUT.

Ultra-wide 10Hz-50kHz frequency RECORDING IS SOMETHING A

WORKSTATION IS NOT GOING TO GIVE YOU. AND THIS MEANS

THAT THIS SYNTH IS CAPABLE OF WORKING

AT VERY HIGH STANDARDS. This is the point. Sinergy is the point. Open

mind. Open system. Open heart. This is the point. Cross platforms linked to each

other. Mutual language. Inter communication

standards. Vst plug in open architecture. A linux system that reads pcs, mac and

android language and runs just the same without any problem. This is the point of

the conversation.
Korg must go OPEN, before its too late, and we have to ask the firm to make this

change if we love them.

And if you want to know what makes the differences, then I will clearly answer,

ideas. Patents.

LIMITLESS inclusion, FROM A SOFTWARE POINT OF VIEW, SO THAT

YOU COULD ADD ANYTHING YOU LIKE TO THE PROGRAMS THAT

YOU ARE RUNNING IN THE SYSTEM.

And finally, you do not need to play your synth with a pc unconfortably set on the

side of your keyboard, because it is inside the keyboard,
and it doing exactly what you are asking it to do, and not playing aabout with dlls,

wifi, spyware etc... let's say shielded.

Take care. If you have not heard about this keyboard it is because most of the

companies oblige sellers not to deal with other companies, ( which is illegal ), but

nevertheless, happens all the time.

I do believe that home made configurations will soon beat standard workstations,

and that their capabilities will be much higher that the ones their redy made

products offer.

Just be patient, and wait for "Hackorg", or build yourself a Neko.

Now concentrate on this.

INSIDE THE BOX DETAILS ON OPEN ARCHITECTURE INSIDE THE

BOX DETAILS ON OPEN ARCHITECTURE INSIDE THE BOX DETAILS

ON OPEN ARCHITECTURE
INSIDE THE BOX DETAILS ON OPEN ARCHITECTURE INSIDE THE

BOX DETAILS ON OPEN ARCHITECTURE INSIDE THE BOX DETAILS

ON OPEN ARCHITECTURE
INSIDE THE BOX DETAILS ON OPEN ARCHITECTURE INSIDE THE

BOX DETAILS ON OPEN ARCHITECTURE INSIDE THE BOX DETAILS

ON OPEN ARCHITECTURE

I guess you would like to know Who these people are.

Limberis, Alexander J.
Bryan, Joseph W.
Ottney, Joanne F.
O'Connell, Steven S.
Bryan, Jr., Marcus K.

These are the creators of the Oasys. THANK THEM.

I WILL GIVE YOU INFORMATIONS THAT YOU MIGHT NOT KNOW,

EVEN IF YOU ARE A PROFESSIONAL HERE.

My point was that Kronos is Oasys II and nohing new has happened since this

patent. Prove it? Ok. That's it.

My conversation and research about Oasys and KRONOS, AND WHAT WILL

COME NEXT articles,
infos and search, IS HERE, and I apologize if I wrote to much about this topic on

my friend's post to answer to his question.

These are their claims:

Here the creators of the OA give an explanation of their invenction.

We claim:

1. An audio signal processor comprising:

an input to supply real time input signals indicating selected voices;

voice program memory to store voice programs for respective voices, the voice

programs comprising sequences of instructions for generation of the respective

voices;

sound processing resources, coupled to the voice program memory and the input,

responsive to real time input signals which execute a group of the voice programs

in the voice program memory to generate

selected voices in real time; and

voice allocation resources, coupled with the input and the voice program memory,

which dynamically allocate a voice program for a selected voice to the group in

response to the real time input signals.

2. The audio signal processor of claim 1, wherein the voice allocation resources

include:

circuitry to replace a particular voice program in the group with a voice program

for a selected voice in response to the real time input signals.

3. The audio signal processor of claim 1, wherein the voice program memory

includes:

a first memory to store a plurality of voice programs; and

a second memory, coupled with the sound processing resources and the first

memory, to store the group of voice programs for execution by the sound

processing resources.

4. The audio signal processor of claim 3, wherein the voice allocation resources

include:

circuitry, coupled with the first and second memories of the voice program

memory, to transfer at least a component of a selected voice program from the

first memory to the second memory in real time.

5. The audio signal processor of claim 1, wherein the sound processing resources

include:

at least one signal processor, coupled to the voice program memory, for executing

voice programs to generate sound data representing the selected voices; and

an audio output, coupled with the at least one signal processor, which produces

audio signals in response to the sound data.

6. The audio signal processor of claim 5, wherein the voice program memory

includes:

a first memory to store a plurality of voice programs, the voice programs including

instructions for execution by the at least one signal processor;

an instruction memory, coupled to the at least one signal processor and the first

memory, to store instructions for the group of voice programs.

7. The audio signal processor of claim 6, wherein the voice allocation resources

include:

circuitry to replace a particular voice program in the group with a voice program

for a selected voice in response to the real time input signals, including logic to

temporarily mask instruction storage locations

storing instructions for the particular voice program in the instruction memory from

execution by the at least one signal processor without effecting execution of

instructions for other voice programs in the group,

and circuitry to transfer instructions for the selected voice program to the

temporarily masked instruction storage locations.

8. The audio signal processor of claim 5, wherein the voice program memory

includes:

a first memory to store a plurality of voice programs, the voice programs including

delay lines; and

a delay line memory, coupled to the at least one signal processor and the first

memory, to store delay lines for the group of voice programs.

9. The audio signal processor of claim 8, wherein the voice allocation resources

include:

circuitry, coupled with the delay line memory, to disable a delay line of the

particular voice program in the delay line memory and set up a delay line for the

selected voice program in the delay line memory in

real time.

10. The audio signal processor of claim 5, wherein the voice program memory

includes:

a first memory to store a plurality of voice programs, the voice programs including

instructions and coefficients for execution by the at least one signal processor;

an instruction memory, coupled to the at least one signal processor and the first

memory, to store instructions for the group of voice programs; and

a coefficient memory, coupled to the at least one signal processor and the first

memory, to store coefficients for the group of voice programs.

11. The audio signal processor of claim 5, wherein the voice program memory

includes:

a first memory to store a plurality of voice programs, the voice programs including

input/output parameters specifying connections among other voice programs in the

group; and

a input/output parameter memory, coupled to the at least one signal processor and

the first memory, to store input/output parameters for the group of voice

programs.

12. The audio signal processor of claim 5, wherein the voice program memory

includes:

a first memory to store a plurality of voice programs, the voice programs including

instructions, input/output parameters specifying connections among the group of

voice programs, coefficients, tables and delay

lines;

an instruction memory, coupled to the at least one signal processor and the first

memory, to store instructions for the group of voice programs;

a input/output parameter memory, coupled to the at least one signal processor and

the first memory, to store input/output parameters for the group of voice

programs;

a delay line memory, coupled to the at least one signal processor and the first

memory, to store delay lines for the group of voice programs;

a coefficient memory, coupled to the at least one signal processor and the first

memory, to store coefficients for the group of voice programs; and

a table memory, coupled to the at least one signal processor and the first memory,

to store table data for the group of voice programs.

13. The audio signal processor of claim 12, wherein the voice allocation resources

include:

circuitry, coupled with the first memory, the instruction memory and the delay line

memory, to transfer instructions, input/output parameters, coefficients and delay

line parameters of a selected voice program

from the first memory to the instruction memory, input/output parameter memory,

coefficient memory and the delay line memory, respectively, in real time.

14. The audio signal processor of claim 13, wherein the voice allocation resources

include:

circuitry to replace a particular voice program in the group with a voice program

for a selected voice in response to the real time input signals, including logic to

temporarily mask instruction storage locations

storing instructions for the particular voice program in the instruction memory from

execution by the at least one signal processor without effecting execution of

instructions for other voice programs in the group,

and circuitry to transfer instructions for the selected voice program to the

temporarily masked instruction storage locations.

15. The audio signal processor of claim 14, wherein the voice allocation resources

further include:

circuitry, coupled with the delay line memory, to clear a delay line of the particular

voice program in the delay line memory and set up a delay line for the selected

voice program in the delay line memory in

response to the delay line parameters in real time.

16. The audio signal processor of claim 1, wherein the input includes a music

keyboard.

17. The audio signal processor of claim 1, wherein the input includes a MIDI

interface.

18. The audio signal processor of claim 1, wherein the voice allocation resources

include logic to partition the sound processing resources into a plurality of voice

program resource groups, and to selectively

disable particular resource groups without interfering with voice programs using

other resource groups in the plurality, and to allocate the selected voice program

to a disabled voice program resource group in

real time.

19. An audio signal processor comprising:

an input to supply real time input signals indicating selected voices;

a host processing system coupled to the input and, including a source of voice

programs which comprise sequences of instructions for generation of

corresponding voices;

voice program memory, coupled with the host processing system, for storing a

group of voice programs;

at least one signal processor, coupled to the voice program memory and the input,

for executing sequences of instructions in voice programs in the group for selected

voices in response to the real time input

data to generate sound data representing the selected voices;

voice allocation resources, coupled with the input, the host processing system and

the voice program memory, which dynamically allocate a voice program for a

selected voice from the source of voice

programs in the host processing system to the group stored in the voice program

memory in response to the real time input signals; and

an audio output, coupled with the at least one signal processor, which produces

audio signals in response to the sound data.

20. The audio signal processor of claim 19, wherein the voice allocation resources

include:

circuitry to replace a particular voice program in the group with a voice program

for a selected voice in response to the real time input signals.

21. The audio signal processor of claim 19, wherein the voice program memory

includes:

a first memory to store a plurality of voice programs, the voice programs including

instructions for execution by the at least one signal processor;

an instruction memory, coupled to the at least one signal processor and the first

memory, to store instructions for the group of voice programs.

22. The audio signal processor of claim 21, wherein the voice allocation resources

include:

circuitry to replace a particular voice program in the group with a voice program

for a selected voice in response to the real time input signals, including logic to

temporarily mask instruction storage locations

storing instructions for the particular voice program in the instruction memory from

execution by the at least one signal processor without effecting execution of

instructions for other voice programs in the group,

and circuitry to transfer instructions for the selected voice program to the

temporarily masked instruction storage locations.

23. The audio signal processor of claim 19, wherein the voice program memory

includes:

a first memory to store a plurality of voice programs, the voice programs including

delay lines; and

a delay line memory, coupled to the at least one signal processor and the first

memory, to store delay lines for the group of voice programs.

24. The audio signal processor of claim 23, wherein the voice allocation resources

further include:

logic, coupled with the delay line memory, to disable a delay line of the particular

voice program in the delay line memory and set up a delay line for the selected

voice program in the delay line memory in real

time.

25. The audio signal processor of claim 19, wherein the voice program memory

includes:

a first memory to store a plurality of voice programs, the voice programs including

instructions and coefficients for execution by the at least one signal processor;

an instruction memory, coupled to the at least one signal processor and the first

memory, to store instructions for the group of voice programs; and

a coefficient memory, coupled to the at least one signal processor and the first

memory, to store coefficients for the group of voice programs.

26. The audio signal processor of claim 19, wherein the voice program memory

includes:

a first memory to store a plurality of voice programs, the voice programs including

input/output parameters specifying connections among other voice programs in the

group; and

a input/output parameter memory, coupled to the at least one signal processor and

the first memory, to store input/output parameters for the group of voice

programs.

27. The audio signal processor of claim 19, wherein the voice program memory

includes:

a first memory to store a plurality of voice programs, the voice programs including

instructions, input/output parameters specifying connections among the group of

voice programs, coefficients, tables and delay

lines;

an instruction memory, coupled to the at least one signal processor and the first

memory, to store instructions for the group of voice programs;

a input/output parameter memory, coupled to the at least one signal processor and

the first memory, to store input/output parameters for the group of voice

programs;

a delay line memory, coupled to the at least one signal processor and the first

memory, to store delay lines for the group of voice programs;

a coefficient memory, coupled to the at least one signal processor and the first

memory, to store coefficients for the group of voice programs; and

a table memory, coupled to the at least one signal processor and the first memory,

to store table data for the group of voice programs.

28. The audio signal processor of claim 27, wherein the voice allocation resources

include:

circuitry, coupled with the first memory, the instruction memory and the delay line

memory, to transfer instructions, input/output parameters, coefficients and delay

line parameters of a selected voice program

from the first memory to the instruction memory, input/output parameter memory,

coefficient memory and the delay line memory, respectively, in real time.

29. The audio signal processor of claim 27, wherein the voice allocation resources

include:

circuitry to replace a particular voice program in the group with a voice program

for a selected voice in response to the real time input signals, including logic to

temporarily mask instruction storage locations

storing instructions for the particular voice program in the instruction memory from

execution by the at least one signal processor without effecting execution of

instructions for other voice programs in the group,

and to allocate instructions for the selected voice program to the temporarily

masked instruction storage locations.

30. The audio signal processor of claim 29, wherein the circuitry to replace a

particular voice program further includes:

logic, coupled with the delay line memory, to clear a delay line of the particular

voice program in the delay line memory and set up a delay line for the selected

voice program in the delay line memory in

response to the delay line parameters in real time.

31. The audio signal processor of claim 19, wherein the input includes a music

keyboard.

32. The audio signal processor of claim 19, wherein the input includes a MIDI

interface.

33. The audio signal processor of claim 19, wherein the host processing system

includes a processor, a processor bus coupled to the processor, and a first

memory coupled to the processor bus; and wherein

the voice program memory includes:

a second memory isolated from the processor bus; and

circuitry, coupled to the processor bus and the second memory, to route host

reads and writes to the second memory, and to transfer voice programs from the

second memory to the plurality of signal

processors independently of the processor.

34. The audio signal processor of claim 33, wherein the data processor includes

resources responsive to the real time input signal to compute parameters used by

the selected voice programs in parallel with

the transferring of voice programs from the second memory.

35. The audio signal processor of claim 19, wherein the voice allocation resources

include logic to partition resources of the at least one signal processor into a

plurality of voice program resource groups, to

selectively disable particular voice programs resource groups without interfering

with other voice programs resource groups in the plurality, and to allocate the

selected voice program to a disabled voice

program resource group in real time.

36. An audio signal processor comprising:

an input to supply real time input signals indicating selected voices;

a host processing system coupled to the input and, including a source of voice

programs which comprise sequences of instructions for generation of

corresponding voices;

storage means, coupled with the host processing system, for storing a group of

voice programs;

a plurality of signal processors, coupled to the storage means and the input means,

to execute voice programs in the group for selected voices in response to the real

time input data to generate sound data

representing the selected voices;

means, coupled with the input means, the host processing system and the storage

means, for dynamically allocating a voice program for a selected voice from the

the source of voice programs in the host

processing system to the group stored in the storage means in response to the real

time input signals;

an audio data bus, coupled to the plurality of signal processors, to communicate

sound data among the plurality of signal processors; and

an audio output, coupled with the audio data bus, to produce audio signals in

response to the sound data on the bus.

37. The audio signal processor of claim 36, wherein the means for dynamically

allocating includes:

means for replacing a particular voice program in the group with a voice program

for a selected voice in response to the real time input signals.

38. The audio signal processor of claim 36, wherein the storage means includes:

a first memory to store a plurality of voice programs, the voice programs including

instructions for execution by at least one signal processor; and

an instruction memory, coupled to the plurality of signal processors and the first

memory, to store instructions for the group of voice programs.

39. The audio signal processor of claim 38, wherein the means for dynamically

allocating includes:

means for replacing a particular voice program in the group with a voice program

for a selected voice in response to the real time input signals, including means for

temporarily masking instruction storage

locations storing instructions for the particular voice program in the instruction

memory from execution by the at least one signal processor without effecting

execution of instructions for other voice programs in

the group, and means for transferring instructions for the selected voice program

to the temporarily masked instruction storage locations.

40. The audio signal processor of claim 36, wherein the storage means includes:

a first memory to store a plurality of voice programs, the voice programs including

delay lines; and

a delay line memory, coupled to at least one signal processor and the first memory,

to store delay lines for the group of voice programs.

41. The audio signal processor of claim 40, wherein the means for dynamically

allocating further includes:

means, coupled with the delay line memory, for disabling a delay line of the

particular voice program in the delay line memory and setting up a delay line for

the selected voice program in the delay line memory

in real time.

42. The audio signal processor of claim 36, wherein the storage means includes:

a first memory to store a plurality of voice programs, the voice programs including

instructions and coefficients for execution by at least one signal processor;

an instruction memory, coupled to the at least one signal processor and the first

memory, to store instructions for the group of voice programs; and

a coefficient memory, coupled to the at least one signal processor and the first

memory, to store coefficients for the group of voice programs.

43. The audio signal processor of claim 36, wherein the storage means includes:

a first memory to store a plurality of voice programs, the voice programs including

input/output parameters specifying connections among other voice programs in the

group; and

a input/output parameter memory, coupled to the at least one signal processor and

the first memory, to store input/output parameters for the group of voice

programs.

44. The audio signal processor of claim 36, wherein the source of voice programs

in the host processing system includes:

a first memory to store a plurality of voice programs, the voice programs including

sequences of instructions, input/output parameters specifying connections among

the group of voice programs, coefficients,

tables and delay lines; and

the storage means includes a plurality of memory modules coupled to

corresponding signal processors in the plurality of signal processors; each memory

module comprising:

an instruction memory, coupled to the corresponding signal processor and the first

memory, to store sequences of instructions for the group of voice programs;

a input/output parameter memory, coupled to the corresponding signal processor

and the first memory, to store input/output parameters for the group of voice

programs;

a delay line memory, coupled to the corresponding signal processor and the first

memory, to store delay lines for the group of voice programs;

a coefficient memory, coupled to the corresponding signal processor and the first

memory, to store coefficients for the group of voice programs; and

a table memory, coupled to the corresponding signal processor and the first

memory, to store table data for the group of voice programs.

45. The audio signal processor of claim 44, wherein the means for dynamically

allocating includes:

means, coupled with the first memory and the plurality of memory modules, for

transferring instructions, input/output parameters specifying connections among the

group of voice programs, coefficients, and

delay line parameters of a selected voice program from the first memory to

selected memory modules in real time.

46. The audio signal processor of claim 45, wherein the means for dynamically

allocating includes:

means for replacing a particular voice program in the group with a voice program

for a selected voice in response to the real time input signals, including means for

temporarily masking instruction storage

locations storing instructions for the particular voice program in the instruction

memory of the selected module from execution by the corresponding signal

processor without effecting execution of instructions

for other voice programs in the group, and means for transferring instructions for

the selected voice program to the temporarily masked instruction storage

locations.

47. The audio signal processor of claim 46, wherein the means for replacing

further includes:

means, coupled with the plurality of memory modules, for clearing a delay line of

the particular voice program in the delay line memory of the selected memory

module and setting up a delay line for the selected

voice program in the delay line memory in response to the delay line parameters in

real time.

48. The audio signal processor of claim 44, wherein the host processing system

includes means for composing a set of voice programs for real time execution; and

the source of voice programs includes a set

memory to store the set of voice programs; and the means for dynamically

allocating includes means for transferring table data for the set of voice programs

to the table memories in the plurality of memory

modules.

49. The audio signal processor of claim 36, wherein the host processing system

includes means for composing a set of voice programs for real time execution; and

the source of voice programs includes a set

memory to store the set of voice programs.

50. The audio signal processor of claim 49, wherein the voice programs in the set

of voice programs include sequences of instructions, input/output parameters

specifying connections among the group of voice

programs, coefficients, tables and delay lines; and

the storage means includes a plurality of memory modules coupled to

corresponding signal processors in the plurality of signal processors; each memory

module comprising:

an instruction memory, coupled to the corresponding signal processor and the first

memory, to store sequences of instructions for the group of voice programs;

a input/output parameter memory, coupled to the corresponding signal processor

and the first memory, to store input/output parameters for the group of voice

programs;

a delay line memory, coupled to the corresponding signal processor and the first

memory, to store delay lines for the group of voice programs;

a coefficient memory, coupled to the corresponding signal processor and the first

memory, to store coefficients for the group of voice programs; and

a table memory, coupled to the corresponding signal processor and the first

memory, to store table data for the group of voice programs.

51. The audio signal processor of claim 50, wherein at least one of the voice

programs in the set includes sound sample data, further including a sample store in

at least one of the memory modules to store

sound sample data for the group of voice programs.

52. The audio signal processor of claim 36, wherein the input includes a music

keyboard.

53. The audio signal processor of claim 36, wherein the input includes a MIDI

interface.

54. The audio signal processor of claim 36, wherein the host processing system

includes a processor, a processor bus coupled to the processor, and a first

memory coupled to the processor bus; and wherein

the storage means includes:

a second memory isolated from the processor bus; and

means, coupled to the processor bus and the second memory, for routing host

reads and writes to the second memory, and for transferring voice programs from

the second memory to the plurality of signal

processors independently of the processor.

55. The audio signal processor of claim 36, wherein the host processing system

includes means responsive to the real time input signal for computing parameters

used by the selected voice programs in parallel

with the transferring of voice programs from the second memory.

56. The audio signal processor of claim 36, wherein the means for dynamically

allocating includes means for partitioning resources of the plurality of signal

processors into a plurality of voice program resource

groups, and means for selectively disabling particular resource groups without

interfering with voice programs using other resource groups in the plurality, and

allocating the selected voice program to a disabled

voice program resource group in real time.


Rolling Eyes Rolling Eyes Embarassed Crying or Very sad Razz Mad Shocked

Confused Cool Laughing Surprised Smile Very Happy GULP!!!

An architecture for a synthesizer of music or other sounds which comprises an

input device which supplies real time input signals indicating selected voices, a

voice program memory which stores voice

programs for respective voices, and a sound processing module including an array

of digital signal processors, which is coupled to the input device and the voice

program memory, and responsive to real time

input signals to execute a group of voice programs in the voice program memory

to generate selective voices in real time. Resources coupled to the input device

and the voice program memory dynamically

assign voice programs for selected voices to the group of voice programs in

response to the real time input signals. Further, resources are available for

replacing a particular voice program in the group with a

voice program for a selected voice in response to the real time input signals. The

voice program memory includes a first memory which stores a plurality of voice

programs, and a second memory which is

coupled to the sound processing module and the first memory, which stores the

group of voice programs for execution by the sound processing module. The

resources for dynamically assigning a voice

program to the group includes a system for transferring a selected voice program

from the first memory to the second memory in real time. An audio output device,

including a speaker, is coupled to the digital

signal processor for producing sound in response to the sound data.


Razz Mad Confused Razz Embarassed Cool Laughing Sad Smile Smile Very

Happy Wink Rolling Eyes Twisted Evil Very Happy


Online data.

References

4984276 Smith Digital signal processing using waveguide networks
5208421 Lisle et al. Method and apparatus for audio editing of MIDI files
5225618 Wadhams Method and apparatus for studying music

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5768628 Jun 16, 1998 Method for providing high quality audio by storing wave

tables in system memory and having a DMA controller on the sound card for

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usage in a wavetable synthesizer Scott, Jeffrey W.

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based on software Shimizu, Masahiro

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method of generating acoustic waveform data Isozaki, Yoshimasa; Masuda,

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Motoichi

6362409 Mar 26, 2002 Customizable software-based digital wavetable

synthesizer Gadre, Sharadchandra H.

7013381 Mar 14, 2006 Function-variable type digital signal processing
Back to top
Jedi Simon
Guest





PostPosted: Thu Oct 24, 2013 7:11 pm    Post subject: The True Story of the Blue Bomber Oasys = Kronos III part Reply with quote

apparatus, and method of and program for controlling the same Yamada, Katsushi

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interfaces through buffer memory using table data having transfer start address

transfer count and unit selection parameter

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hardware sound sources Wachi, Masatada; Yamada, Hideo; Hirano, Masashi

5744739 Apr 28, 1998 Wavetable synthesizer and operating method using a

variable sampling rate approximation Jenkins, Michael V.

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5852251 Dec 22, 1998 Method and apparatus for real-time dynamic midi control

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hardware sound sources Wachi, Masatada; Yamada, Hideo; Hirano, Masashi

5596159 Jan 21, 1997 Software sound synthesis system O'Connell, Steven S.

5787407 Jul 28, 1998 Data processing system for evaluating fuzzy logic rules and

method therefor Viot, J. Greg

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performance Henderson, William

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distribution medium therefor Yamanoue, Kaoru

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a computer system Priem, Curtis

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So now, You know a little more about your instrument.
You should say Thanks to the people I listed above.
All you need is love.
Why did you chose disergy instead? Money? Business?
Names, numbers, patents and ideas maje the difference most of the time.
Attitudes, some other times.
Kronos is simply the Blue Bomber Oasys, and we are in need of a new magic

keyboard that will astonish and change musical standards.
I'm asking you to face the truth. No need to buy patents here and there just to sell

something.
You must sotp thinking in a disergic way, and practice interlinking.

Teach your machine love, and you will be happy one day.
Selfishness does not pay for long.

Jedi Simon

WHAT KORG IS GOING TO PRODUCE IN THE FUTURE WHAT KORG

IS GOING TO PRODUCE IN THE FUTURE WHAT KORG IS GOING TO

PRODUCE IN THE FUTURE
WHAT KORG IS GOING TO PRODUCE IN THE FUTURE WHAT KORG

IS GOING TO PRODUCE IN THE FUTURE WHAT KORG IS GOING TO

PRODUCE IN THE FUTURE
WHAT KORG IS GOING TO PRODUCE IN THE FUTURE WHAT KORG

IS GOING TO PRODUCE IN THE FUTURE WHAT KORG IS GOING TO

PRODUCE IN THE FUTURE

So to answer to yor question, Here is what is going to come next from Korg.

Now I will tell you what they are thinking about, and what they would like to sell

in the future.

The original post question was :
I wonder what will ever come along to surpass OASYS?
and I am answering here not to disturb their thoughts there.

This one, and do not ask me how do I know, because I eat patents at breakfast

time on toast.

. A system for creating and manipulating digital media, comprising: a graphics

tablet comprising a tablet surface, a grid of wires located under the tablet surface,

and a graphics tablet chipset comprising: a

graphics tablet chipset interface operably connected to the grid of wires for

sending power to a stylus when the stylus is positioned over the tablet surface and

receiving a signal from the stylus; and a graphics

tablet chipset output; wherein the graphics tablet chipset determines a position of

the stylus with respect to the tablet surface using the graphics tablet chipset

interface, and outputs the position of the stylus to

the graphics tablet chipset output; a touchpad being positioned on the tablet

surface such that the touchpad also detects the position of the stylus

simultaneously with the graphics tablet determining the position

of the stylus; a synthesizer chipset comprising: a synthesizer chipset input in

communication with the touchpad; and a synthesizer chipset sound output; wherein

the synthesizer chipset creates digital sounds

based on input from the touchpad via the synthesizer chipset input, and outputs the

digital sounds to the synthesizer chipset sound output; and a computer having a

graphical user interface (GUI), the GUI being

in communication with the graphics tablet chipset output for receiving the position

of the stylus from the graphics tablet chipset; wherein the computer has a sound

input in communication with the synthesizer

chipset output for receiving the digital sounds from the synthesizer chipset, wherein

the computer executes a sound manipulation software program for manipulating

the digital sounds to produce manipulated

digital sounds, and wherein the computer further has a sound output for outputting

the manipulated digital sounds; wherein the computer executes a drawing software

program for: creating a visual image using

the position of the stylus from the graphics tablet chipset as an input to the drawing

software program; and influencing characteristics of the visual image using the

digital sounds from the synthesizer chipset; and

wherein the computer further has a video output for outputting the visual image.

2. The system of claim 1, further comprising a housing containing the graphics

tablet, the touchpad and the synthesizer chipset in a unitary assembly.

3. The system of claim 2, further comprising: a program/value input device being

integral with the housing; a program/value display device being integral with the

housing; and a loop function input device being

integral with the housing; and wherein the synthesizer chipset further comprises: a

program/value input in communication with the program/value input device, for

receiving a selection of one of a plurality of

synthesized sound programs for creating the digital sounds; a program/value

display output in communication with the program/value display device, for

displaying an indication of the selection of one of the

plurality of synthesized sound programs; and a loop function input in

communication with the loop function input device for receiving an instruction to

stack sound phrases from at least two of the plurality of

synthesized sound programs.

4. The system of claim 3, further comprising a strap having a first end and a

second end, the first end and the second end attached to the housing so that the

housing can be supported by a body of a user when

creating the digital sounds.

5. The system of claim 1, wherein the stylus further has an integral loop function

input device, and wherein the synthesizer chipset further comprises a loop function

input in communication with the loop function

input device for receiving an instruction to stack sound phrases from at least two

of a plurality of synthesized sound programs.

6. The system of claim 1, wherein the computer has a sound input in

communication with the synthesizer chipset output for receiving the digital sounds

from the synthesizer chipset, wherein the computer

executes a sound manipulation software program for manipulating the digital

sounds to produce manipulated digital sounds, and wherein the computer further

has a sound output for outputting the manipulated

digital sounds.

7. The system of claim 1, wherein the computer executes a drawing software

program for creating a visual image using the position of the stylus from the

graphics tablet chipset as an input to the drawing

software program, and wherein the computer further has a video output for

outputting the visual image.

8. A system for creating and manipulating digital media, comprising: a graphics

tablet comprising a tablet surface, a grid of wires located under the tablet surface,

and a graphics tablet chipset comprising: a

graphics tablet chipset interface operably connected to the grid of wires for

sending power to a stylus when the stylus is positioned over the tablet surface and

receiving a signal from the stylus; and a graphics

tablet chipset output; wherein the graphics tablet chipset determines a position of

the stylus with respect to the tablet surface using the graphics tablet chipset

interface, and outputs the position of the stylus to

the graphics tablet chipset output; a touchpad being positioned on the tablet

surface such that the touchpad also detects the position of the stylus

simultaneously with the determination of the position of the

stylus by the graphics tablet; and a switch being interfaced to the touchpad for

switching the touchpad between a first touchpad interface, a second touchpad

interface, and a standby position; a first synthesizer

chipset comprising: a first synthesizer chipset input in communication with the first

touchpad interface; and a first synthesizer chipset sound output; a second

synthesizer chipset comprising: a second synthesizer

chipset input in communication with the second touchpad interface; and a second

synthesizer chipset sound output; wherein the first synthesizer chipset and the

second synthesizer chipset create first synthesizer

digital sounds and second synthesizer digital sounds, respectively, based on input

from the touchpad via the first synthesizer chipset input and the second synthesizer

chipset input, respectively, and output the

first synthesizer digital sounds and the second synthesizer digital sounds to the first

synthesizer chipset sound output and the second synthesizer chipset sound output,

respectively; and an audio mixer

comprising: a first channel input to a first channel in communication with the first

synthesizer chipset sound output; a second channel input to a second channel in

communication with the second synthesizer

chipset sound output; a mixing control; and an audio mixer output; wherein the

audio mixer mixes the first synthesizer digital sounds and the second synthesizer

digital sounds via the mixing control to produce

mixed digital sounds, and outputs the mixed digital sounds to the audio mixer

output.

9. The system of claim 8, further comprising a housing containing the graphics

tablet, the touchpad, the switch, the first synthesizer chipset, the second

synthesizer chipset, and the audio mixer in a unitary

assembly.

10. The system of claim 9, further comprising: a first program/value input device

being integral with the housing; a first program/value display device being integral

with the housing; a first loop function input

device being integral with the housing; a second program/value input device being

integral with the housing; a second program/value display device being integral

with the housing; and a second loop function

input device being integral with the housing; wherein the first synthesizer chipset

further comprises: a first program/value input in communication with the first

program/value input device, for receiving a selection

of one of a plurality of synthesized sound programs of the first synthesizer chipset

for creating the first synthesizer digital sounds; a first program/value display output

in communication with the first

program/value display device, for displaying an indication of the selection of one of

the plurality of synthesized sound programs of the first synthesizer chipset; and a

first loop function input in communication

with the first loop function input device for receiving an instruction to stack sound

phrases from at least two of the plurality of synthesized sound programs of the first

synthesizer chipset; and wherein the second

synthesizer chipset further comprises: a second program/value input in

communication with the second program/value input device, for receiving a

selection of one of a plurality of synthesized sound programs of

the second synthesizer chipset for creating the second synthesizer digital sounds; a

second program/value display output in communication with the second

program/value display device, for displaying an

indication of the selection of one of the plurality of synthesized sound programs of

the second synthesizer chipset; and a second loop function input in communication

with the second loop function input device

for receiving an instruction to stack sound phrases from at least two of the plurality

of synthesized sound programs of the second synthesizer chipset.

11. The system of claim 10, further comprising a strap having a first end and a

second end, the first end and the second end attached to the housing so that the

housing can be supported by a body of a user.

12. The system of claim 8, further comprising a computer having a graphical user

interface (GUI), the computer being in communication with the graphics tablet

chipset output, the computer receiving the

position of the stylus from the graphics tablet chipset as an input to the GUI.

13. The system of claim 12, wherein the computer has a sound input in

communication with the audio mixer output for receiving the mixed digital sounds

from the audio mixer output, wherein the computer

executes a sound manipulation software program for manipulating the mixed digital

sounds to produce manipulated digital sounds, and wherein the computer further

has a sound output for outputting the

manipulated digital sounds.

14. The system of claim 12, wherein the computer executes a drawing software

program for creating a visual image using the position of the stylus from the

graphics tablet chipset as an input to the drawing

software program, and wherein the computer further has a video output for

outputting the visual image.

15. The system of claim 12, wherein the computer has a sound input in

communication with the audio mixer output for receiving the mixed digital sounds

from the audio mixer output, wherein the computer

executes a sound manipulation software program for manipulating the mixed digital

sounds to produce manipulated digital sounds, and wherein the computer further

has a sound output for outputting the

manipulated digital sounds; wherein the computer executes a drawing software

program for: creating a visual image using the position of the stylus from the

graphics tablet chipset as an input to the drawing

software program; and influencing characteristics of the visual image using the

mixed digital sounds from the audio mixer output; and wherein the computer

further has a video output for outputting the visual

image.

16. The system of claim 8, wherein the stylus further comprises a first integral loop

function input device and a second integral loop function input device; wherein the

first synthesizer chipset further comprises a

first loop function input in communication with the first integral loop function input

device for receiving an instruction to stack sound phrases from at least two of a

plurality of synthesized sound programs of the

first synthesizer chipset; and wherein the second synthesizer chipset further

comprises a second loop function input in communication with the second integral

loop function input device for receiving an

instruction to stack sound phrases from at least two of a plurality of synthesized

sound programs of the second synthesizer chipset.

A system for creating and manipulating digital media integrates a graphics tablet, a

touchpad, and a synthesizer chipset. The graphics tablet includes a tablet surface,

a grid of wires located under the tablet

surface, and a graphics tablet chipset. The graphics tablet chipset includes an

interface operably connected to the grid of wires for sending power to a stylus

when the stylus is positioned over the tablet surface

and receiving a signal from the stylus used to determine a position of the stylus

with respect to the tablet surface. The touchpad is positioned on the tablet surface

such that the touchpad also detects the position

of the stylus simultaneously with the graphics tablet. The synthesizer chipset

creates digital sounds based on input from the touchpad. The position of the stylus

is output to a graphics tablet chipset output, and

the digital sounds are output to a synthesizer chipset sound output.


Second concept.

A method for generating a new recording of a past musical performance of a

musician from a recording of the past musical performance, the past musical

performance having associated acoustics based on a

setting of the past musical performance, comprising: obtaining a high-resolution

data record representing actions of the musician while playing the past musical

performance that is generated based on the

recording of the past musical performance, wherein the high-resolution data

record is an anacoustic data record that is free of the acoustics of the past musical

performance; positioning an automated musical

instrument in a selected acoustic context; positioning a sound detection device at a

selected sound detection location in the selected acoustic context; providing the

high-resolution data record to the musical

instrument to cause the musical instrument to re-produce the actions of the

musician while playing the past performance; and recording, using the sound

detection device, sound waves generated by the musical

instrument while the actions of the musician are being re-produced to generate the

new recording of the past musical performance.

2. The method of claim 1, wherein the high-resolution data record comprises

notes played by the musician during the past musical performance detected based

on sound waves generated by the musician

during the past musical performance and wherein the high-resolution data record

includes at least four associated characteristics for each note.

3. The method of claim 1, wherein obtaining the high-resolution data record

comprises generating the high-resolution data record based on an audio recording

of the sound waves generated by the musician

while playing the past musical performance.

4. The method of claim 3, wherein generating the high-resolution data record

comprises detecting notes played by the musician during the past musical

performance based on the sound waves generated by the

musician during the past musical performance and providing at least four

associated characteristics for each detected note.

5. The method of claim 4, wherein an instrument played by the musician while

playing the past musical performance comprises a piano and wherein the at least

four associated characteristics at least one

hammer positioning characteristic and at least one pedal positioning characteristic.

6. The method of claim 5, wherein the at least four associated characteristics

include pitch, timing and at least one of volume, hammer velocity, a key release

characteristic, a key release timing, a key angle

when pressed characteristic, damper positions and/or pedal positions.

7. The method of claim 6, wherein ones of the at least four associated

characteristics associated with timing are provided with at least milli-second timing

resolution.

8. The method of claim 1, wherein recording the sound waves is followed by

generating a high-resolution data record representing actions of the musical

instrument to re-produce the actions of the musician by

detecting notes played by the musical instrument while re-producing the actions of

the musician based on the recorded sound waves generated by the musical

instrument and providing at least four associated

characteristics for each detected note.

9. The method of claim 1, wherein obtaining a high-resolution data record

comprises obtaining a plurality of high-resolution data records, wherein positioning

the automated musical instrument comprises

positioning a plurality of automated musical instruments and wherein providing the

high-resolution data record to the musical instrument comprises providing

respective ones of the plurality of high-resolution

data records to corresponding ones of the automated musical instruments.

10. The method of claim 1, wherein positioning the automated musical instrument

in the selected acoustic context is preceded by selecting the desired acoustic

context for the new recording and wherein

positioning the sound detection device is preceded by selecting the desired sound

detection location in the selected acoustic context.

11. The method of claim 1, wherein the high-resolution data record comprises

notes played by the musician during the past musical performance detected based

on sound waves generated by the musician

during the past musical performance, wherein the high-resolution data record

includes at least four associated characteristics for each note and wherein

providing the high-resolution data record to the musical

instrument is preceded by modifying the high-resolution data record.

12. The method of claim 11, wherein modifying the high-resolution data record

comprises changing notes, phrasing, emphasis and/or pedaling associated

characteristics for the notes played by the musician.

13. The method of claim 11, wherein modifying the high-resolution data record

comprises changing notes, phrasing, emphasis, articulation and/or pedaling

associated characteristics for the notes played by the

musician.

14. The method of claim 1, wherein the sound detection device comprises a

plurality of sound detection devices and wherein the selected sound detection

location comprises a plurality of locations selected to

provide for stereo, surround sound or binaural playback of the new recording of

the past musical performance.

15. The method of claim 14, wherein recording sound waves comprises recording

sounds with different ones of the plurality of sound detection devices to generate a

plurality of new recordings associated

respectively with stereo, surround sound and/or binaural playback.

16. The method of claim 1, wherein the musical instrument comprises a virtual

musical instrument, the sound detection device comprises a virtual sound detection

device, the acoustic location comprises a

virtual acoustic location, the actions of the musician comprise algorithmic

simulations to define virtual sound waves and the sound waves comprise the virtual

sound waves and wherein a software regeneration

module carries out positioning the automated musical instrument in the selected

acoustic context, positioning the sound detection device at the selected sound

detection location in the selected acoustic context,

providing the high-resolution data record to the musical instrument to cause the

musical instrument to re-produce the actions of the musician while playing the past

performance and recording the sound waves

to generate the new recording of the past musical performance.

17. A computer system for generating a new recording of a past musical

performance of a musician from a recording of the past musical performance, the

past musical performance having associated acoustics

based on a setting of the past musical performance, comprising: a source high-

resolution data record representing actions of the musician while playing the past

musical performance that is generated based on

the recording of the past musical performance, wherein the high-resolution data

record is an anacoustic data record that is free of the acoustics of the past musical

performance; and a regeneration module that

is configured to: position a virtual musical instrument in a selected virtual acoustic

context; position a virtual sound detection device at a selected virtual sound

detection location in the selected virtual acoustic

context; input the source high-resolution data record to the virtual musical

instrument to simulate the actions of the musician while playing the past

performance to produce virtual sound waves and to save the

virtual sound waves as detected by the virtual sound detection device to generate

a new recording file based on the source high-resolution data record.

Methods for generating a new recording of a past musical performance of a

musician from a recording of the past musical performance include obtaining a

high-resolution data record representing actions of the

musician while playing the past musical performance that is generated based on the

recording of the past musical performance and positioning an automated musical

instrument in a selected acoustic context and

a sound detection device at a selected sound detection location in the selected

acoustic context. The high-resolution data record is provided to the musical

instrument to cause the musical instrument to re-

produce the actions of the musician while playing the past performance. Sound

waves generated by the musical instrument are recorded while the actions of the

musician are being re-produced to generate the

new recording of the past musical performance.


Third concept

A musical instrument comprising: a sound chamber and a neck attached to the

sound chamber, a fingerboard disposed along a portion of the neck, the sound

chamber and neck defining a longitudinal axis; a

plurality of strings positioned above the sound chamber and fingerboard, the

strings oriented along the longitudinal axis; an electronic device contained within or

on the instrument, the electronic device

generating output upon activation by a user, wherein the electronic device is

removably attached to a mounting plate, wherein the electronic device comprises

an outer housing having a magnet attached thereto,

and the magnet attaches to a metallic member of the mounting plate; and the

fingerboard comprising a top surface and edge surfaces on either side of the top

surface, the fingerboard further comprising a

plurality of position markers flushly mounted within the top surface or one of the

edge surfaces, the position markers of the type which provide an indication of a

location for the user's fingers on the fingerboard

to produce one or more particular tones from the strings, wherein one or more of

the position markers comprises means for illuminating upon receiving output from

the electronic device.

2. The musical instrument of claim 1 wherein the musical instrument comprises a

guitar.

3. The musical instrument of claim 1 wherein the electronic device is connected to

one or more light emitting diodes wherein each light emitting diode comprises a

top surface and the position markers comprise

the top surface of the light emitting diode.

4. The musical instrument of claim 1 wherein the electronic device comprises a

housing having one or more light emitting diodes wherein each light emitting diode

comprises a top surface, and a first end of a

fiber optic cable is abutted against the top surface, wherein the fiber optic cable

comprises a second end, wherein the second end comprises an illuminating

position marker.

5. The musical instrument of claim 1 wherein the electronic device is a digital tuner.

6. The musical instrument of claim 5 wherein the digital tuner illuminates a first light

emitting diode if an inputted tone is flat, illuminates a second light emitting diode if

an inputted tone is sharp, and illuminates a

third light emitting diode if an inputted tone is in tune.

7. The musical instrument of claim 6 wherein the light emitting diodes comprise a

top surface and the position markers comprise the top surfaces of the first light

emitting diode, the second light emitting diode,

and the third light emitting diode.

8. The musical instrument of claim 6 wherein a first end of a first fiber optic cable

is abutted against the first light emitting diode, a first end of a second fiber optic

cable is abutted against the second light

emitting diode, and a first end of a third fiber optic cable is abutted against the

third light emitting diode, wherein the first fiber optic cable, the second fiber optic

cable and the third fiber optic cable each

comprise a second end, and the position markers respectively comprise the

second ends of the first fiber optic cable, the second fiber optic cable, and the

third fiber optic cable.

9. The musical instrument of claim 1 wherein the electronic device comprises a

remotely actuated control switch.

10. The musical instrument of claim 1 wherein the electronic device is contained

within the sound chamber.

11. A musical instrument comprising: a sound chamber and a neck attached to the

sound chamber, a fingerboard disposed along a portion of the neck, the sound

chamber and neck defining a longitudinal axis; a

plurality of strings positioned above the sound chamber and fingerboard, the

strings oriented along the longitudinal axis; an electronic device contained within or

on the instrument, the electronic device

generating output upon activation by a user, the electronic device comprising a

housing having one or more light emitting diodes wherein each light emitting diode

comprises a top surface; a first end of a fiber

optic cable abutted against the top surface of each light emitting diode, wherein the

fiber optic cable comprises a second end; the fingerboard comprising a top

surface and edge surfaces on either side of the

top surface, the fingerboard further comprising a plurality of position markers

flushly mounted within the top surface or one of the edge surfaces, the position

markers of the type which provide an indication of a

location for the user's fingers on the fingerboard to produce one or more particular

tones from the strings, wherein one or more of the position markers comprises the

second end of a fiber optic cable.

12. The musical instrument of claim 11 wherein the sound chamber comprises a

soundboard, and the electronic device is contained within the sound chamber.

13. The musical instrument of claim 12 wherein the fiber optic cable is routed

through the soundboard and through the neck.

14. The musical instrument of claim 11 wherein the electronic device is a digital

tuner.

15. The musical instrument of claim 14 wherein the digital tuner illuminates a first

light emitting diode if an inputted tone is flat, illuminates a second light emitting

diode if an inputted tone is sharp, and illuminates

a third light emitting diode if an inputted tone is in tune.

16. The musical instrument of claim 15 wherein a first end of a first fiber optic

cable is abutted against the first light emitting diode, a first end of a second fiber

optic cable is abutted against the second light

emitting diode, and a first end of a third fiber optic cable is abutted against the

third light emitting diode, wherein the first fiber optic cable, the second fiber optic

cable and the third fiber optic cable each

comprise a second end, and the position markers respectively comprise the

second ends of the first fiber optic cable, the second fiber optic cable, and the

third fiber optic cable.

17. The musical instrument of claim 15 wherein the digital tuner comprises a

remotely actuated control switch.

18. The musical instrument of claim 14 wherein the digital tuner is removably

attached to a mounting plate contained within the sound chamber.

A stringed musical instrument has a sound chamber and a neck attached to the

sound chamber. A fingerboard is attached along the neck. The musical instrument

has an electronic device such as a chromatic

tuner or a preamplifier, which is either mounted inside or on the exterior of the

musical instrument. The fingerboard has a plurality of position markers which are

flush with an edge face of the fingerboard. One

or more of the position markers illuminates to display output from the electronic

device. The position marker may either be the top of a light emitting diode

attached to the electronic device, or the position

marker may be the terminating end of a length of fiber optic cable, where the

opposite end of the fiber optic cable abuts a light emitting diode mounted within

the housing of the electronic device.


This is the direction Korg makers are going. I suppose that I could even be more

precise than this if I wanted to, but I am aware that your limits have been

surpassed and that there is no use in doing this.

I was only answering to freinds who asked me to clear out a few points, and

giving them tangible proof of what I know, and examples of what I was talking

about in other posts.


Concerning Oasys, the Blue Bomber, that is infact in my opinion Kronos

Keyboard, i guess that you will find most of the patents of the Oasys in it.

So, to speak clearly, i do no think that there as been a true evolution, or cultural

evolution in it, rather than a reduction of the global costs, materials, ready made

software, and cheaper hard disks and memory
banks.

You get what you pay.

I'm sorry I'm made a mess writing bits and pieces here and there.
Find your way out if you are not interested in what I am writing,
and please, do not post less that 100 lines, if you want me to answer to you,

because I have no time for personal and subjective thoughts about people, what

they think or believe, like or dislike, from a personal point of view, since science

and scientific matters are something we should face whitout prejudice. My goal is

to make Korg produce a Magical Keyboard again. Ibelieve in miracles. If you

have any other piece of information to add, articles, data, tech specs etc... please

partecipate.


That's all foks.


Take care.

Jedi Simon
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SanderXpander
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Joined: 29 Jul 2011
Posts: 7860

PostPosted: Thu Oct 24, 2013 7:40 pm    Post subject: Reply with quote

You rape science with everything you say so I think our personal opinions are just as valid as yours. Some might argue more valid. This is an internet forum, after all.

Still, I'm enjoying it, so please continue. I can use some levity in my life from time to time.
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cello
Platinum Member


Joined: 11 Jun 2009
Posts: 2152
Location: Glasgow, UK

PostPosted: Thu Oct 24, 2013 7:52 pm    Post subject: Reply with quote

Help ma kilt - I've seen it all now.

What's wrong with a company re-using their IP, supported by their patents? Every company in the world does that - otherwise what's the point in being innovative?

Believe me I am no fan of the tacky Kronos or how Korg treated OASYS owners, however Korg has every right to deploy their patents as they see fit.

End of.
_________________
Plugged in: Fantom 8, Jupiter 80, System-8, JD-XA, V-Synth GTv2, FA-06, SE-02, JU-06A (on order), MX-1, TR-9, TR-8, VT-3, KRK Rokit 5, Cakewalk by Bandlab
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Jedi Simon
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PostPosted: Thu Oct 24, 2013 8:05 pm    Post subject: Nothing wrong. Perfect Reply with quote

Nothing wrong my dear. Keep using your patent, but buy a new one, and
go for it. This was the point. Pefect surplace.
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Jedi Simon
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PostPosted: Thu Oct 24, 2013 8:22 pm    Post subject: Still waiting for the snowball effect.... Reply with quote

Still waiting for the snowball effect....

Snowball effect is a figurative term for a process that starts from an initial state of small significance and builds upon itself, becoming larger (graver, more serious), and also perhaps potentially dangerous or disastrous (a vicious circle, a "spiral of decline"), though it might be beneficial instead (a virtuous circle). This is a very common cliché in cartoons and modern theatrics and it is also used in Psychology.

The common analogy is with the rolling of a small ball of snow down a snow-covered hillside. As it rolls the ball will pick up more snow, gaining more mass and surface area, and picking up even more snow and momentum as it rolls along.

In aerospace engineering, it is used to describe the multiplication effect in an original weight saving. A reduction in the weight of the fuselage will require less lift, meaning the wings can be smaller. Hence less thrust is required and therefore smaller engines, resulting in a greater weight saving than the original reduction. This iteration can be repeated several times, although the decrease in weight for each iteration decreases.

The startup process of a feedback electronic oscillator, when power to the circuit is switched on, is a technical application of the snowball effect. Electronic noise is amplified by the oscillator circuit and returned to its input filtered to contain primarily the selected (desired) frequency, gradually getting stronger in each cycle, until a steady-state oscillation is established, when the circuit parameters satisfy the Barkhausen stability criterion.

I was just hoping to create a black hole.

Do you like Dominoes?

Jedi
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Jedi Simon
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PostPosted: Thu Oct 24, 2013 8:43 pm    Post subject: When I smoke... Reply with quote

In electronics, the Barkhausen stability criterion is a mathematical condition to determine when a linear electronic circuit will oscillate. It was put forth in 1921 by German physicist Heinrich Georg Barkhausen (1881–1956).

It is widely used in the design of electronic oscillators, and also in the design of general negative feedback circuits such as op amps, to prevent them from oscillating.

Barkhausen's criterion applies to linear circuits with a feedback loop. Therefore it cannot be applied to one port negative resistance active elements like tunnel diode oscillators.

It states that if A is the gain of the amplifying element in the circuit and β(jω) is the transfer function of the feedback path, so βA is the loop gain around the feedback loop of the circuit, the circuit will sustain steady-state oscillations only at frequencies for which:

The loop gain is equal to unity in absolute magnitude, that is, |\beta A| = 1\,;
The phase shift around the loop is zero or an integer multiple of 2π: \angle \beta A = 2 \pi n, n \in 0, 1, 2,\dots\,.

Barkhausen's criterion is a necessary condition for oscillation but not a sufficient condition: some circuits satisfy the criterion but do not oscillate.

Similarly, the Nyquist stability criterion also indicates instability but is silent about oscillation. Apparently there is not a compact formulation of an oscillation criterion that is both necessary and sufficient.

Barkhausen's original "formula for self-excitation", intended for determining the oscillation frequencies of the feedback loop, involved an equality sign: |βA| = 1. At the time conditionally-stable nonlinear systems were poorly understood; it was widely believed that this gave the boundary between stability (|βA| < 1) and instability (|βA| ≥ 1), and this erroneous version found its way into the literature.[4] However, stable oscillations only occur at frequencies for which equality holds.

The Nyquist stability criterion, discovered by Swedish-American electrical engineer Harry Nyquist at Bell Telephone Laboratories in 1932,[1] is a graphical technique for determining the stability of a system. Because it only looks at the Nyquist plot of the open loop systems, it can be applied without explicitly computing the poles and zeros of either the closed-loop or open-loop system (although the number of each type of right-half-plane singularities must be known). As a result, it can be applied to systems defined by non-rational functions, such as systems with delays. In contrast to Bode plots, it can handle transfer functions with right half-plane singularities. In addition, there is a natural generalization to more complex systems with multiple inputs and multiple outputs, such as control systems for airplanes.

While Nyquist is one of the most general stability tests, it is still restricted to linear, time-invariant systems. Non-linear systems must use more complex stability criteria, such as Lyapunov or the circle criterion. While Nyquist is a graphical technique, it only provides a limited amount of intuition for why a system is stable or unstable, or how to modify an unstable system to be stable. Techniques like Bode plots, while less general, are sometimes a more useful design tool.

A Bode plot (/ˈboʊdi/ is a graph of the transfer function of a linear, time-invariant system versus frequency, plotted with a log-frequency axis, to show the system's frequency response. It is usually a combination of a Bode magnitude plot, expressing the magnitude of the frequency response gain, and a Bode phase plot, expressing the frequency response phase shift.

Among his several important contributions to circuit theory and control theory, engineer Hendrik Wade Bode (1905–1982), while working at Bell Labs in the United States in the 1930s, devised a simple but accurate method for graphing gain and phase-shift plots. These bear his name, Bode gain plot and Bode phase plot.

The magnitude axis of the Bode plot is usually expressed as decibels of power, that is by the 20 log rule: 20 times the common (base 10) logarithm of the amplitude gain. With the magnitude gain being logarithmic, Bode plots make multiplication of magnitudes a simple matter of adding distances on the graph (in decibels), since

\log(a \cdot b) = \log(a) + \log(b).\

A Bode phase plot is a graph of phase versus frequency, also plotted on a log-frequency axis, usually used in conjunction with the magnitude plot, to evaluate how much a signal will be phase-shifted. For example a signal described by: Asin(ωt) may be attenuated but also phase-shifted. If the system attenuates it by a factor x and phase shifts it by −Φ the signal out of the system will be (A/x) sin(ωt − Φ). The phase shift Φ is generally a function of frequency.

Phase can also be added directly from the graphical values, a fact that is mathematically clear when phase is seen as the imaginary part of the complex logarithm of a complex gain.

The magnitude and phase Bode plots can seldom be changed independently of each other — changing the amplitude response of the system will most likely change the phase characteristics and vice versa. For minimum-phase systems the phase and amplitude characteristics can be obtained from each other with the use of the Hilbert transform.

If the transfer function is a rational function with real poles and zeros, then the Bode plot can be approximated with straight lines. These asymptotic approximations are called straight line Bode plots or uncorrected Bode plots and are useful because they can be drawn by hand following a few simple rules. Simple plots can even be predicted without drawing them.

The approximation can be taken further by correcting the value at each cutoff frequency. The plot is then called a corrected Bode plot.

The Bode plotter is an electronic instrument resembling an oscilloscope, which produces a Bode diagram, or a graph, of a circuit's voltage gain or phase shift plotted against frequency in a feedback control system or a filter. An example of this is shown in Figure 10. It is extremely useful for analyzing and testing filters and the stability of feedback control systems, through the measurement of corner (cutoff) frequencies and gain and phase margins.

This is identical to the function performed by a vector network analyzer, but the network analyzer is typically used at much higher frequencies.

Analog signal processing is any signal processing conducted on analog signals by analog means. "Analog" indicates something that is mathematically represented as a set of continuous values. This differs from "digital" which uses a series of discrete quantities to represent signal (see digital signal processing). Analog values are typically represented as a voltage, electric current, or electric charge around components in the electronic devices. An error or noise affecting such physical quantities will result in a corresponding error in the signals represented by such physical quantities.

Examples of analog signal processing include crossover filters in loudspeakers, "bass", "treble" and "volume" controls on stereos, and "tint" controls on TVs. Common analog processing elements include capacitors, resistors, inductors and transistors.

A system's behavior can be mathematically modeled and is represented in the time domain as h(t) and in the frequency domain as H(s), where s is a complex number in the form of s=a+ib, or s=a+jb in electrical engineering terms (electrical engineers use j because current is represented by the variable i). Input signals are usually called x(t) or X(s) and output signals are usually called y(t) or Y(x).

Convolution is the basic concept in signal processing that states an input signal can be combined with the system's function to find the output signal. It is the integral of the product of two waveforms after one has reversed and shifted; the symbol for convolution is *.

y(t) = (x * h )(t) = \int_{a}^{b} x(\tau) h(t - \tau)\, d\tau

That is the convolution integral and is used to find the convolution of a signal and a system; typically a = -∞ and b = +∞.

Consider two waveforms f and g. By calculating the convolution, we determine how much a reversed function g must be shifted along the x-axis to become identical to function f. The convolution function essentially reverses and slides function g along the axis, and calculates the integral of their (f and the reversed and shifted g) product for each possible amount of sliding. When the functions match, the value of (f*g) is maximized. This occurs because when positive areas (peaks) or negative areas (troughs) are multiplied, they contribute to the integral.

Sinusoids are the building block of analog signal processing. All real world signals can be represented as an infinite sum of sinusoidal functions via a Fourier series. A sinusoidal function can be represented in terms of an exponential by the application of Euler's Formula.

An impulse (Dirac delta function) is defined as a signal that has an infinite magnitude and an infinitesimally narrow width with an area under it of one, centered at zero. An impulse can be represented as an infinite sum of sinusoids that includes all possible frequencies. It is not, in reality, possible to generate such a signal, but it can be sufficiently approximated with a large amplitude, narrow pulse, to produce the theoretical impulse response in a network to a high degree of accuracy. The symbol for an impulse is δ(t). If an impulse is used as an input to a system, the output is known as the impulse response. The impulse response defines the system because all possible frequencies are represented in the input

A unit step function, also called the Heaviside step function, is a signal that has a magnitude of zero before zero and a magnitude of one after zero. The symbol for a unit step is u(t). If a step is used as the input to a system, the output is called the step response. The step response shows how a system responds to a sudden input, similar to turning on a switch. The period before the output stabilizes is called the transient part of a signal. The step response can be multiplied with other signals to show how the system responds when an input is suddenly turned on.

The unit step function is related to the Dirac delta function by;

\mathrm{u}(t) = \int_{-\infty}^{t} \delta (s)ds

Linearity means that if you have two inputs and two corresponding outputs, if you take a linear combination of those two inputs you will get a linear combination of the outputs. An example of a linear system is a first order low-pass or high-pass filter. Linear systems are made out of analog devices that demonstrate linear properties. These devices don't have to be entirely linear, but must have a region of operation that is linear. An operational amplifier is a non-linear device, but has a region of operation that is linear, so it can be modeled as linear within that region of operation. Time-invariance means it doesn't matter when you start a system, the same output will result. For example, if you have a system and put an input into it today, you would get the same output if you started the system tomorrow instead. There aren't any real systems that are LTI, but many systems can be modeled as LTI for simplicity in determining what their output will be. All systems have some dependence on things like temperature, signal level or other factors that cause them to be non-linear or non-time-invariant, but most are stable enough to model as LTI. Linearity and time-invariance are important because they are the only types of systems that can be easily solved using conventional analog signal processing methods. Once a system becomes non-linear or non-time-invariant, it becomes a non-linear differential equations problem, and there are very few of those that can actually be solved.

Signal processing is an area of systems engineering, electrical engineering and applied mathematics that deals with operations on or analysis of analog as well as digitized signals, representing time-varying or spatially varying physical quantities. Signals of interest can include sound, electromagnetic radiation, images, and sensor readings, for example biological measurements such as electrocardiograms, control system signals, telecommunication transmission signals, and many others.

The goals of signal processing can roughly be divided into the following categories.

Signal acquisition and reconstruction, which involves measuring a physical signal, storing it, and possibly later rebuilding the original signal or an approximation thereof. For digital systems, this typically includes sampling and quantization.
Quality improvement, such as noise reduction, image enhancement, and echo cancellation.
Signal compression (Source coding), including audio compression, image compression, and video compression.
Feature extraction, such as image understanding and speech recognition.

Seismic signal processing

In communication systems, signal processing may occur at OSI layer 1, the Physical Layer (modulation, equalization, multiplexing, etc.) in the seven layer OSI model, as well as at OSI layer 6, the Presentation Layer (source coding, including analog-to-digital conversion and signal compression).

Digital signal processing is the processing of digitized discrete-time sampled signals. Processing is done by general-purpose computers or by digital circuits such as ASICs, field-programmable gate arrays or specialized digital signal processors (DSP chips). Typical arithmetical operations include fixed-point and floating-point, real-valued and complex-valued, multiplication and addition. Other typical operations supported by the hardware are circular buffers and look-up tables. Examples of algorithms are the Fast Fourier transform (FFT), finite impulse response (FIR) filter, Infinite impulse response (IIR) filter, and adaptive filters such as the Wiener and Kalman filters.

Nonlinear signal processing involves the analysis and processing of signals produced from nonlinear systems and can be in the time, frequency, or spatio-temporal domains. Nonlinear systems can produce highly complex behaviors including bifurcations, chaos, harmonics, and subharmonics which cannot be produced or analyzed using linear methods.

This is something you should truly investigate.

Jedi
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Jedi Simon
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PostPosted: Fri Oct 25, 2013 9:03 am    Post subject: Inside Job. Oasys patents. Reply with quote

Inside the box.

Only add pure data here and tech specs please.
No personal comments on me and personal thoughts about what I say
if you are not going to add any scientific content that would help me and you to understand better our instrument.

Do not waste your time reading these posts if you feel disturbed by them.

I will answer to 100 lines replies, and not to nonsense, so just avoid posting silly one sentence answers here, and write them in your own post.

Quite a few internet opinion makers engines practice this, so forgive them, because most of the shitty things you might find here, and obviously hylarious ones, are in fact machine made to build up other people ideas. Chat engines do this job. So, just read the technical data.
I apologize for the dust, but this is inevitable in public forums of thhis kind. Mank kind made comments of this kind are most of the time made in opposition to some information that the boss of the company usually dislikes, and this is a protocol, that does not belong to internet culture itself, but to politics, science, culture, information, knowledge, etc... proxy pinged like/dislike values are in fact controlled to address people towards a specific target. Think about the keyboard you own. Don't you think that to use all this incredible know how only to compose a song, it would be terrible waste? It is, I assure you. They are infact using Closed Architecture Systems and protocols in your society. Think about being a single note of the harmony. Thiat's it. You got the picture. And so where does all this chaos come from, if we consider this advanced and perfect system? It simply comes from running things in a disergic way, just to create problems that we have to solve later on. This is the game that is slowing down progress, and inevitably making all the systems collapse under the weight of inefficency.

Think it as a TRON machine. We have the possibility to do things in a better way today. Lets do them.
Think about an integrated circuit. Perfection. Think about urbanism and you city. Traffic jam.
See the difference? Very limited efficency is what they offer all the time. This is why we should cooperate to make a change.
Ask for something better. Go OPEN AND AIR. Cloud and internet are powerful communicating means that we should use properly.
Give me a religion, and I will pray for your God. Give me a workstation, and I will express my feelings in the ways you allow me to do.
It's no a Combi affair, it a synergic machine I am talking about, vital, intelligent and ready to dialogue with other machines, systems, accept programmation, run engines and understand my needs, and give me the possibility to create what I feel like, and not what I have to.
Squared minds, make squared instruments. Music has a lot to do with the creative principle, and this one is a feminine one. It gives birth, rather than repeating the same paths all the time, in a jojo game, ritual, rite, mantra, karmic circle, that is in fact the ultimate cage or toy that they gave you to play with. God knows what creation is, and the Architect is a professional that tries to do the same, but unfortunately, his limits are the one of his generation and wishes. It could have been better, but let's go back to data mining and see what there is inside the box.

Here you have it. This is what there is inside the box.

There are a number of music synthesizer architectures in common use. These include subtractive synthesis, wave table synthesis, F/M synthesis, and additive synthesis. A brief discussion of these common synthesis formats is provided in Walker, Korg Wavestation, Peter L. Alexander Publishing Inc., Newbury Park, Calif., 1990, pages 9 through 22. All of these four common synthesis types rely on playing back packaged waveforms, which may be manipulated in real time by the user to generate voices of the synthesizer. The packaged waveforms may consist of simple sine waves, as in the subtractive and FM synthesis formats, or on tables of actual recorded music from real instruments. The tables are typically stored in a compressed format known as Pulse Code Modulation (PCM) on memory chips in the synthesizer circuitry.

The prior art synthesizers based on playback techniques have somewhat limited range of voices that may be created by the instrument. To change the voices available on a given instrument, new sampling hardware must be added, in the form of new PCM tables, or the like.

There is a growing trend in the music synthesizer industry to synthesize sounds using sound generating programs executed by digital signal processors (DSPs). Since programming can be conducted by individual programmers who may not have access to the hardware resources necessary to update a sampling based synthesizer, users of the DSP synthesizers have much greater flexibility in the voices that may be played by their instrument.

These sound generating programs, called voice programs, are based on computational models of musical instruments, the human voice or other sound source. Thus the developer of a sound generating program typically first defines a computational model of the sound source he or she desires to create, and then writes a computer program to execute the model. Prior art examples of such sound generating programs are described in U.S. Pat. No. 4,984,276, invented by Julius O. Smith, entitled "DIGITAL SIGNAL PROCESSING USING WAVEGUIDE NETWORKS."

Dynamic voice allocation in an electronic musical instrument implies the ability to activate an arbitrary sound using whatever sound generation resources (e.g. memory, processors, bus cycles, etc.) are required, regardless of whether or not the resources are currently available. This means if resources are available, they are used immediately, and if resources are not available, they must be "stolen" from whatever voice is currently using them and reallocated to the new voice.

In typical playback based synthesizers, dynamic voice allocation is made possible by restricting the variation of the voice resource requirements to a very limited set that can be changed within a small time interval. Typically this is accomplished by making every voice use the same algorithm (which is usually built into dedicated hardware), share the same PCM data, use the same amounts of memory, and connect to the output using a fixed configuration audio bus. In this scenario, the only differences between voices are a few data values that can be initialized and changed quickly. If resources are not available, they can be made available using "voice stealing" that shuts down an active voice to allow resources allocated to it to be used by a new voice. One prior art system, known as the DPM-3, manufactured by Peavy, uses a DSP engine to execute a voice program. To dynamically change the voice, coefficients used by the single voice program are changed in real time. However, the instructions of the voice program itself cannot be changed in real time, which limits the flexibility of the system.

More recently, variable algorithm DSP systems have been added to some of these playback synthesizers that allow different audio effects processing to be applied to the signals generated by the fixed architecture voice system. However, the effects processing cannot be changed in real time because of the time it takes to make all the necessary changes in the DSP system to ready it for the new algorithm(s).

Synthesizers designed to execute voice programs utilize powerful digital signal processors to execute in real time. The real time systems have been limited in the number of voices that may be executed in real time, by the resources of the digital signal processor. All the real time voices have to be preloaded in the digital signal processor instruction space. If a voice that was not preloaded needed to be played in real time, an audible interruption of the executing program would occur so that the time consuming process of clearing delay lines, updating tables, initializing coefficients, and supplying the program itself could be carried out. Further, this process was required to displace a voice program already loaded in the instruction space of the DSP, which could cause further audible interruptions or clicks in the output of the machine.

Therefore, prior art DSP based systems have been unable to provide for dynamic voice allocation to the output channels of the synthesizer, as available in sampling or playback based systems.

Accordingly, there is a need to provide for dynamic voice allocation in digital signal processing based music synthesizer systems.
SUMMARY OF THE INVENTION

The present invention provides for dynamic voice allocation in a digital signal processing based music synthesizer or other audio signal processor. According to the present invention, an architecture for an audio signal processor comprises an input device which supplies real time input signals indicating selected voices, a voice program memory which stores voice programs for respective voices, and a sound processing module which is coupled to the input device and the voice program memory, and responsive to real time input signals, to execute a group of voice programs in the voice program memory to generate selected voices in real time. Resources coupled to the input device and the voice program memory dynamically allocate voice programs for selected voices to the group of voice programs in response to the real time input signals. Further, resources are available for replacing a particular voice program in the group with a voice program for a selected voice in response to the real time input signals.

The voice program memory according to one aspect of the invention includes a first memory which stores a plurality of voice programs, and a second memory which is coupled to the sound processing module and the first memory, which stores the group of voice programs for execution by the sound processing module. The resources for dynamically allocating a voice program to the group includes a system for transferring a selected voice program from the first memory to the second memory in real time.

The sound processing module according to the present invention includes at least one digital signal processor, which executes voice programs in the voice program memory to generate sound data representing the selected voices. An audio output device, including digital to analog converters and a speaker, is coupled to the digital signal processor for producing sound in response to the sound data.

The voice programs include instructions, initializing coefficients, tables, and delay lines. The memory which is connected to the sound processing module includes instruction memory coupled to at least one digital signal processor to store instructions for the group of voice programs, a delay line memory coupled to at least one digital signal processor to store delay lines for the group of voice programs, and a table memory coupled to at least one digital signal processor to store table data for the group of voice programs.

The resources for dynamically allocating voices include apparatus for transferring instructions and delay line parameters of a selected voice program from the first memory to the instruction memory and the delay line memory respectively in real time. In order to replace a particular voice program in a group, the instruction storage locations for the particular voice program are temporarily masked in the instruction memory from execution by the digital signal processor without affecting execution of other voice programs in the group. The instructions for the selected voice program are transferred into the temporarily masked instruction storage location for dynamic allocation of the selected voice program.

The resources for replacing a particular voice program also include a mechanism for clearing a delay line of a particular voice program in the delay line memory and setting up a delay line for the selected voice program in the delay line memory in response to the delay line parameters in real time.

Accordingly, another aspect of the invention, the sound processing module includes an input device, a host processing system, which includes resources for supplying voice programs for generation of corresponding voices, and a storage unit for storing a group of voice programs. A plurality of digital signal processors is coupled to the storage unit and the input device for executing selected voices from the group of voice programs in response to real time input data. An audio data bus is coupled to the plurality digital signal processors for communicating sound data among the digital signal processors, and an audio output structure, including a digital to analog converter, produces sound in response to the sound data on the bus. Resources for dynamically allocating voice programs for selected voices to the group stored in the storage unit in response to the real time input signals are provided as described above.

The storage unit includes a plurality of memory modules coupled to corresponding digital signal processors. Each memory module includes an instruction memory, a delay line memory, and a table memory for the corresponding digital signal processor.

According to another aspect, the host processing system includes a program for composing a set of voice programs for real time execution. The set of voice programs are stored in a set memory in a format which facilitates the dynamic allocation of voices to the storage unit coupled to the plurality digital signal processors. In this system, the table memory in each memory module of the storage unit stores table data for the entire set of voice programs. Instructions for dynamically allocated voice programs are loaded using the temporary masking technique described above. Delay line memory for the dynamically allocated voices are also updated using the real time clearing mentioned above.

The host system according to another aspect of the invention is optimized for dynamic allocation of voice programs to the sound processing module. In this aspect, the host system includes a CPU with main memory, and a isolated memory. The isolated memory is coupled to the CPU with an interface that allows the host independent transfer of data from the isolated memory to the sound processing module for dynamic allocation of voices. The host system composes a set of voice programs by storing them in a format optimized for transfers to the sound processing module into the isolated memory. In response to real time input signals indicating a selected voice from the set of voice programs, the interface chip through automatic DMA transfers assigns the selected voice program to a memory module in the sound processing module.

The present invention provides a digital signal processing based synthesizer/audio processing system having the unique capability of being able to reconfigure itself extremely quickly in order to generate musical signals in response to real time control information from a keyboard, modulation controllers, standard MIDI inputs etc. The system is designed around an array of digital signal processors with both hardware and software enhancements which allow it to work in real time. The system enables dynamic voice allocation in a digital signal processing based electronic music synthesizer, between voices requiring differing digital signal processing algorithms for execution.

Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description and the claims which follow.

Then they gave the commission 20 images to show them what they were talking about.

FIG. 1 is a conceptual block diagram of a music synthesizer according to the present invention.

FIG. 2 is a hardware block diagram of a main central processing unit block for a system shown in FIG. 1.

FIG. 3 is a hardware block diagram for a human interface block for use with the CPU shown in FIG. 2.

FIG. 4 is a hardware block diagram of a music signal processing (MSP) module and output structure for use with the system of FIGS. 2 and 3.

FIGS. 5-1 and 5-2 are a functional block diagram of the system integration chip of FIG. 2.

FIGS. 5A through 5K illustrate register configurations for the system integration chip of FIGS. 5-1 and 5-2.

FIG. 6 is a functional block diagram of an individual music signal processor in the system of FIG. 4.

FIG. 6A is a block diagram showing the MSP windowing scheme.

FIG. 6B is a chart illustrating the MSP conditional execution scheme.

FIG. 6C is a block diagram of the high speed audio bus interface HSAB of the MSP.

FIG. 6D is a chart illustrating the MSP delay line and table management scheme.

FIG. 6E is a logic diagram of the RAM addressing block of the MSP.

FIG. 7 provides memory and hardware model of the dynamic voice allocation system according the present invention.

FIG. 8 is an overview block diagram of the voice allocation processing sequence according to the present invention.

FIG. 9 is a flow chart for the JOB DISPATCHER for use in the system of FIG. 7.

FIG. 10 is a flow chart for the NOTE ON routine called by the JOB DISPATCHER of FIG. 9.

FIG. 11 is a flow chart for the NOTE DONE sub-routine called by the JOB DISPATCHER of FIG. 9.

FIG. 12 is a flow chart for the PROGRAM CHANGE sub-routine called by the JOB DISPATCHER of FIG. 9.

FIG. 13 is a flow chart for the SET BUILD sub-routine called by the JOB DISPATCHER routine of FIG. 9.

FIG. 14 is a flow chart for the ALLOCATE VOICE routine called by the NOTE ON routine of FIG. 10.

FIG. 15 is a flow chart for the SET BUILD VERIFY sub-routine called by the PROGRAM CHANGE routine of FIG. 12.

FIG. 16 is the flow chart for CREATE VOICE sub-routine called in the SET BUILD routine of FIG. 13.

FIG. 17 is a flow chart for SHUT DOWN VOICE sub-routine called by the ALLOCATE VOICE sub-routine of FIG. 14.

FIG. 18 is a flow chart for INIT/START UP VOICE sub-routine called by the ALLOCATE VOICE sub-routine of FIG. 14.

FIG. 19 illustrates voice program images in the isolated host memory for the system of FIG. 7.

FIG. 20 illustrates the voice program images for a group of a voice programs stored in the MSP memory for the system of FIG. 7.

Then, they had to explain in detail every image, one by one.


DETAILED DESCRIPTION

A detailed description of the preferred embodiments of the present invention is provided with respect to the Figs. FIG. 1 provides a heuristic overview of the present invention. FIGS. 2 through 6, and 6A through 6E illustrate a specific hardware implementation of the synthesizer. FIGS. 7 through 20 illustrate the operation of dynamic voice allocation according to the present invention.
I. Overview (FIG. 1)

FIG. 1 provides an overview block diagram of a music synthesizer with dynamic voice allocation according to the present invention. The invention may also be applied to other audio signal processors, like mixers or effects processors. The synthesizer includes an input device 10, a host processor module 11 including host memory and dynamic voice allocation resources, and a music signal processor module 12 which includes MSP memory and dynamic voice allocation resources. The music signal processor 12 generates an analog output on line 13 which is supplied through amplifier 21 to speakers 14 and 15 to generate real time sound. Besides analog sound signals, other audio signal types, such as digital sound data, in standard or non-standard formats may be used as well. The input device 10 may be a music keyboard or other device as known in the art. Other input signals may be supplied from a variety of sources, such as the MIDI standard format for musical instruments on line 16. The system also provides for accepting analog input signals on line 17 for digitizing and supply to the music signal processor module 12.

The host processor module 11 provides a plurality of voice programs stored in the host memory. Also, the host processor module 11 accepts input signals from the input device 10 or from the input channel 16 for controlling allocation and production of voices in the music signal processor module 12.

In the music signal processor module, MSP memory stores a group of voice programs for active execution by the module. This group of voice programs utilizes the memory resources of the music signal processor 12 for instructions, delay lines, tables, coefficients and the like for active programs. The dynamic voice allocation resources in the host processor module 11 and the MSP processor module 12 provide for allocation and de-allocation of voice programs to the music signal processor module 12 in response to input signals supplied by the keyboard 10 or by the MIDI input channel 16 or by host programs.

The music signal processor module 12 may have a plurality of output channels, e.g., 32, corresponding to particular voices being executed at the same time. If a new voice must be allocated in response to an input signal to one of the available channels, each channel is updated with digital signal data at an audio rate, combined with the output of other channels, and supplied to a digital to analog converter to generate analog output sound on line 13 for supply to the speakers 14 and 15.

Each channel actively utilizes a set of instructions in the instruction memory associated with the music signal processor module for supplying the output data. When a new voice is to be allocated to one of the channels, the instructions, coefficients, tables and delay lines in the music signal processor for the selected voice must be moved into the music signal processor, and any particular voice program which is being replaced by the selected voice program must be de-allocated--delay lines cleared, coefficients overwritten, instructions masked and the like--without causing an audible glitch in the output signal. Each channel can be considered the result of a corresponding voice program. Thus for a 32 channel system, 32 voice programs may be allocated to the group of voice programs which are actively being executed at a given time.

To dynamically allocate a voice, a voice program must be moved from host memory in the host processor module to the MSP memory in the MSP module 12 in real time, and without significant glitch in the audio output. For the purposes of this application, real time is considered limited by the perception of the user of the input device 10. Thus, such user must strike a key to select a voice, the selected voice must be allocated to the group of voice programs in the MSP memory, and the music signal processor must execute the voice without a perceptible delay or other distortion in the audio output.

The primary hardware modules in a synthesizer for accomplishing dynamic voice allocation include the host processor module 11, the music signal processor module 12 and the input device 10. A preferred implementation of these systems is provided below with respect to FIGS. 2 through 6.

This is how a patent presentation works.

II. Hardware System (FIGS. 2-4)

The host processor module 11, input device 10, and music signal processor module 12 of a preferred hardware system are described in detail with respect to FIGS. 2, 3 and 4, respectively.

FIG. 2 is schematic diagram of the host processor module with resources for dynamic voice allocation according to the present invention. The main CPU system consists of a microprocessor 50 such as a Motorola 68340 coupled to a 16 bit data bus 51 and a 23 bit address bus 52. Also control signals on line 53 and clock signals on line 54 are driven by the CPU 50. A crystal oscillator 55 is coupled to the CPU for providing reference for the clock signal 54.

The address, control, and data buses 51, 52, 53 are coupled to a floppy controller 56 and a floppy disk drive 57, to a SCSI interface controller 58 and a SCSI interface 59 and to a time of day clock chip 60. Time of day clock is connected to a battery 61 and a crystal 62 for providing clock reference. A DUART interface 63 is coupled to secondary data bus 70, the control bus 53 and the address bus 52 for use in as a debug interface.

Data line 51 is coupled to bus transceiver 71, which drives the secondary bus 70 for peripheral devices coupled to the main CPU 50. Transceiver control is supplied on line 72 from a system integration chip 73.

The system integration chip 73 also provides addressing logic, decoding logic, DRAM control, MSP windowing logic, interrupt management, MSP DMA logic, and LCD control to integrate the system as described in more detail with reference to FIG. 5.

A power supply 64 coupled to a wall outlet across line 65 supplies power throughout the system as necessary as indicated by arrow 66. Also an on/off switch 67 is coupled to the power supply. A program store 68 consisting of EPROM is also coupled to bus 70, control lines 52 and address lines 52 for use by the CPU 50.

A main system memory 75 consists of from 1 to 5 megabytes of DRAM with such expansion slots 76 and 77 as desired. The system memory 75 is coupled to the data bus 51, and to an address 78 and a control bus 79 which are driven by the system integration chip 73. An isolated memory bank 80 consisting of DRAM is also coupled to the system integration chip 73 by means of address lines 81 and control lines 82. Data is supplied on line 83 to the isolated memory 80 from the system integration chip 73. System integration chip 73 also generates address information on lines 84 and control information on lines 85 for supply together with data on line 83, to the MSP module of FIG. 4. Thus, a host interface 110 to the MSP module of FIG. 4 includes address lines 84, control lines 85 and data lines 83.

The system integration chip 73 is also coupled to a independent clock 66. System integration chip 73 also generates a clock signal on line 87 and drives a serial interface 88 providing for communication to the human interface module FIG. 3.

The main CPU block also includes hardware for serving the human interface module through connections 102. This hardware includes an LCD controller 89 which receives control information from the system integration chip 73 across line 90 and data from bus 70. The output of an address/data multiplexer 91 is supplied to the LCD controller 89. The inputs to the address/data multiplexer 91 include the address bus 52 and the data bus 70. Also, the address and data multiplexer 91 is coupled to an SRAM 92 for use in driving the LCD controller 89. The LCD display memory on the human interface block is time multiplexed between the LCD controller 89 and the CPU 50. The LCD controller has priority over the CPU. If the CPU tries to access the LCD SRAM 92 at the same time as the LCD controller, the control logic generates wait states for CPU.

The CPU memory organization provides for main memory 75 and isolated memory 80. The isolated memory 80 is used for data that will be written to the MSPs using the DMA logic on the system integration chip 73. This data can be transferred to the MSPs while the main memory 75 is being accessed by the CPU 50. This memory access pipeline speeds up the initialization and downloading of voice programs to the MSPs.

The CPU 50 is also coupled to a MIDI port 93 across serial input line 94 and serial output line 95. An additional serial output line 96 is coupled to a 1 to 2 multiplexer 97 which drives a serial output line 98 or serial output line 96 with data from line 100 in response to a selection control signal line 99. The data on line 100 is driven by the CPU 50. Serial input line 101 is received by the CPU 50 from the human interface module of FIG. 3.

As can be see, an interface 102 to the human interface module of FIG. 3 includes a serial output line 98, a serial input line 101, an LCD control signal on line 103 from LCD controller 89, a clock signal on line 87, and a 4 bit serial interface on line 88.

FIG. 3 shows the human interface module coupled to the interface 102 of FIG. 2. The serial output on line 98 and serial input on line 101 are coupled to a touch screen sub-system controller 120 which overlays a backlit LCD array 121. The backlit LCD array 121 is driven by signals on line 103 from the LCD controller 89. Clock signals on line 87 are coupled to a keyboard scanning processor 122. Also, the keyboard scanning processor 122 drives serial interface 88. A number of input devices are coupled to the scanning processor 122 including a rotary encoder 123, an XYZ control pad 124, an array of LEDs 125, an array of buttons 126, a music keyboard such as a 76 note keyboard 127, an after touch detector 128, a set of control wheels 129, a set of data sliders 130, a number of foot peddle inputs 131, and a ribbon controller 132. The keyboard scanning processor performs all keyboard, front panel button, analog controller, and rotary encoder scanning. It also drives LEDs coupled with the buttons and a serial interface 88 to the system integration chip 73 in the main CPU block.

FIG. 4 illustrates the music signal processor module for use with the system of FIG. 2. The system includes an array of digital signal processors 150-0 through 150-8. Thus, there are 9 digital signal processors in the system described in FIG. 4. This configuration may be expanded or reduced as suits the needs of a particular application.

Each of the digital signal processors according to the preferred implementation of the present invention is a music signal processor MSP implemented as described with reference to FIG. 6 below. The MSP is a digital signal processor which has certain enhancements to support the dynamic allocation of voice programs according to the present invention.

The array of digital signal processors 150-0 through 150-8 are all coupled in parallel to the address lines 84, control lines 85 and data lines 83 on the host system interface 110.

Also coupled to each MSP 150-0 through 150-8 is a memory module. MSP 150-0 includes expanded memory module 151. MSPs 150-1 through 150-8 include standard memory modules 152-1 through 152-8. The plurality of MSPs 150-0 through 150-8 in the array are coupled to a high speed audio bus 153. The high speed audio bus is coupled to digital to analog and analog to digital interface 154. Outputs from the bus are supplied to one of two digital to analog converters 155 or 156. The output of digital to analog converter 155 is supplied to respective left and right filters 157, 158 through master volume control 159 to output jacks 160 for the left and 161 for the right. Also, a headphone jack 162 is provided at the output of the master volume control 159. The digital to analog converter 156 drives left and right outputs thought filters 163 and 164 to auxiliary outputs 165 and 166 respectively. Analog input signals are supplied on inputs 167 and 168 through an analog to digital converter 169 to the bus interface chip 154, for transmission on the bus 153 to a target MSP. Clock 170 drives the interface chip 154.

As can be seen, in the system including a main CPU block of FIG. 2, the human interface block of FIG. 3, and the music signal processing block of FIG. 4 provide a digital signal processor based music synthesizer which executes a group of voice programs stored in instruction memory of MSPs 150-0 to 150-8 and the memory modules 151 and 152-1 through 152-8 in real time. A set of voice programs are composed and stored in the isolated memory 80 which may be dynamically allocated to the memory modules in the MSP array of FIG. 4. The host CPU is used to compose voice programs or receive them from external sources, and load them into the isolated memory 80 for dynamic allocation. The host processing system also provides such support processing as necessary to handle MIDI standard interfaces, and control functions for the human interface block.
III. The System Integration Chip (SIC) (FIG. 5-1 and 5-2)

FIG. 5-1 and 5-2 provide a functional block diagram of the system integration chip SIC. The system integration chip has a host CPU interface generally at 500, a main non-isolated DRAM interface generally 501, an isolated DRAM interface generally 502, an MSP interface generally 503, a peripheral control interface generally 504, a serial interface generally 505, and receives error signals and interrupt signals generally 506 from the MSP array. It also generates clocks generally 507 for use in the system.

The CPU interface 500 is primarily coupled to CPU interface control block 508. Also, data from the CPU interface 500 is supplied on line 509 to transceivers 510 and to serial interface control and registers 511. The data is also supplied to DMA control registers 513. The chip includes address multiplexers 514 and non-isolated DRAM control 515 for the non-isolated DRAM interface 501. Also, address multiplexers 516 isolated DRAM control 517 and transceivers 510 supply such control, address and data as necessary for the isolated DRAM interface 502. Address multiplexers 518, MSP bus interface control logic 519 and MSP window register 520 are used to supply such address and control information as is necessary for the MSP interface 503. The SIC chip also generates an interrupt signal on line 512 for the CPU interface 500.

The MSP data from the isolated DRAM interface 502 is also coupled directly to the MSP interface 503 as illustrated in FIG. 2.

The SIC chip further provides peripheral bus control 521. A clock generation block 522 is responsive to the host system clock to generate the clock signals 507. An MSP interrupt register 523 receives interrupt data from the MSP array and supplies SIC interrupt logic 524 which drives the SIC interrupt signal 512. An SIC mask register 525 is used to mask unused interrupts. A refresh request logic 526 is used for refresh control of the DRAMs. The MSP-DRAM DMA controller 527 is coupled to the isolated DRAM control 517 and the MSP bus interface 519 for controlling DMA transfers into the isolated DRAM, and into the MSP interface. The DMA controller 527 is coupled to the DMA control registers 513 to generate CPU DRAM addresses for supply to the address multiplexers 516 for the isolated DRAM interface, and MSP addresses for supply to the address multiplexers 516 for the isolated DRAM interface, and MSP addresses for supply to the address multiplexers 518 for supply to the MSP interface 503. Also, mapped addresses are supplied by the CPU interface control to the address multiplexers 514, 516, and 518.

More details concerning the function of elements of the SIC are provided below.
A. The CPU Interface Control Block 508

The CPU interface control block 508 provides address decoding, external bus transceiver control, chip select generation, wait state generation, DSACK generation for the host CPU, address inversion for the chip select area 3 as described below, and bus error generation. It also provides control signals for the non-isolated DRAM control 515, the isolated DRAM control 517, the MSP bus interface control, and the peripheral bus interface control.
B. CPU Address Space Decoding

The SIC and the 68340 CPU chip select registers determine the system memory map. The CPU Interface Control 508 decodes the 68340 address bus using the ASL and CS0L-CS3L signals, and generates chip select and control signals for the DRAM and peripherals.

Each DRAM is tied to one of the four chip-select (CS) regions. That is, both the CS signal and the address bus must be active for the address to be decoded and the cycle to be performed by the SIC.

After system initialization, the system logical memory space is divided into four regions: read-only (CS2L), read/write (CS1L), virtual page (CS0L), and fast negative RAM (CS3L). The operations of these regions are controlled by registers in the 68340. For example, the read-only action is programmed in the 68350, and not in the SIC. The same is true for the virtual page areas, explained below.

Wait states for the peripheral devices are generated when necessary by the SIC based on the address decode.
1. BERRL (Bus Error) Signal Generation

The BERRL signal will be asserted by CAU interface control 508 in two situations: the ASL line is asserted and none of the CS0L-CS3L lines are asserted, or the CS1L line is asserted with improper address.
2. Chip Select Area Zero Operation

The 68340 global chip select, CS0L, is used for either the EPROM 68 or the virtual page chip select. When the 68340 begins fetching after reset; CS0L is asserted for every address until the module base address register is accessed. The 68340 signal PORTA0 and the PA0 signal input to the SIC determine which is selected. After reset, the PORTA0 signal is configured as an input pin. An external pull-down resistor on the PORTA0 pin will pull the signal low, selecting the EPROM. After system initialization is complete, the PORTA0 pin will be high to disable the EPROM and enable the virtual page chip select. See below concerning virtual page operation. When the EPROM is selected, the SIC responds with DSACKs for an 8-bit area. When the EPROM is selected, the SIC responds with DSACKs for an 8-bit area. When the virtual page mode is operating, the SIC responds to byte and word accesses.
3. Chip Select Area One Operation

This region is activated by the CS1L signal, and is assigned to the entire physical RAM and the area of physical memory used for hardware I/O operations. This includes the Floppy Controller 56, the SCSI bus controller 58, the Real time clock 60, the DUART 63, the LCD controller 89 and LCD display RAM 92, the individual MSPs and the MSP window area (in DRAM 80).

This region also contains the address decoding for most of the isolated and non-isolated DRAM within the system. A small, variable amount of the physical RAM is assigned to the CS2L region, explained below.
4. Chip Select Area Two Operation

This area is activated by the CS2L signal from the 68340 CPU. It contains the fast-negative RAM area, which can be accessed quickly due to the way the 68340 (and other processors) calculate indirect memory accesses. There is no logic in the SIC which makes the bus cycle "fast" or "negative". The time saved is only in the 68340's address calculations.
5. Virtual Page Operation

The virtual pages are to be used to implement a simple but effective overlay manager. The overlays are compiled to operate in one of the page regions in the 68340's logical address space. The overlays will each be coded to appear in one of the 64 KB logical page spaces, but are loaded from disk into the same physical space.

When the program tries to call a function/procedure/subroutine in an overlay not currently loaded, the address will be in some other (logical) page area. The SIC will assert the BERRL line, and the overlay manager software in the 68340 will be alerted.

The overlay manager will then remap the physical area to the needed logical page area by moving the address decode area for the CS0L signal. The new overlay is then retrieved from disk onto the page area, and the original program continues. This occurs each time a "page fault" occurs, and each time a (currently unloaded) overlay is needed.
C. CPU Bus Control

The CPU Interface Control 508 determines the port size and controls the termination of all 68340 external bus cycles. During a transfer cycle, the SIC signals the port size and indicates completion of the bus cycle to the 68340 through the use of the DSACK0L and DSACK1L outputs. Refer to the MC68340 Integrated Processor User's Manual and Technical Summary for more details on the 68340 bus operation.
1. Bus Transceiver Control

The CPU Interface control 508 generates control signals for the external bus transceiver 71 that can be connected between the 68340's primary data bus and the peripheral data bus.
D. CPU Interrupt Control

The SIC Interrupt Logic 524 provides one active-low, level sensitive hardware interrupt on line 512 to the 68340. The SIC also provides 9 external MSP interrupt request inputs to register 523, and three internal interrupt request sources. All are software maskable by the Interrupt Mask Register 525. The SIC provides internal pull-up resistors on the MSP interrupt request inputs. Following one or more interrupt requests, the SIC issues the SIC.sub.-- IRQL signal to the 68340. The CPU determines the source of the interrupt by reading the SIC Interrupt Status Register. The MSP interrupt requests can only be cleared by reading the MSP status registers in the MSPs. The rest of the SIC interrupt requests are cleared by reading the SIC status register. SIC.sub.-- IRQL remains asserted until all interrupt requests have been cleared.
E. EPROM Support

The 32K.times.8 CPU EPROM 68 interfaces directly to the 68340 address bus, global chip select (CS0L), and PORTA0 pin. When the EPROM is selected, the SIC returns DSACK0L within two wait states, providing a five-clock bus cycle access. The 68340 global chip select, CS0L, is used for both the EPROM and the virtual page chip selects.
F. DRAM Support

The SIC provides access and refresh control for the two areas of system DRAM 75, 80. The basic configuration consists of 1 MB DRAM for CPU operating system code (non-Isolated DRAM 175) and 1 MB for MSP programs and data storage (isolated DRAM 80). The SIC provides for expansion of the non-isolated DRAM for a total of 5 MB. The SIC provides separate control, and address buses for each of the two areas of system DRAM. The SIC DMA controller 527 provides DMA transfers from the system isolated DRAM to the MSP internal and DRAM areas. This allows the CPU to operate at full speed during downloads to the MSPs.
1. Non-Isolated DRAM Controller

The Non-Isolated DRAM controller 515 supports both CPU and refresh cycles. The SIC provides all control signals required for the 68340 CPU to read or write data with zero wait states (three-clock bus cycle). The SIC supports both 8 and 16-bit CPU accesses to the system DRAM.

DRAM refresh is accomplished by means of a CAS before RAS refresh cycle, refreshing all three rows of non-isolated DRAM simultaneously. The DRAM controller executes a refresh cycle after any current bus access once a request is generated by the DRAM refresh counter. In the non-isolated memory area, refresh has the highest priority. If a CPU cycle is in progress when a refresh request is generated, the refresh controller will wait until the current cycle is finished. The refresh cycle will then be performed. If the CPU requests access to the non-isolated RAM while the refresh cycle is operating, it must wait until the refresh cycle is finished.
2. Isolated DRAM Controller 517

The isolated DRAM controller 517 supports CPU, refresh, and DRAM-to-MSP DMA cycles.

A CPU access to the isolated DRAM is identical to an access to the non-isolated DRAM. The MGC provides all control signals required for the 68340 CPU to read or write data with zero wait states (three-clock bus cycle). The MGC supports both 8 and 16-bit CPU accesses to the system DRAM.

DRAM refresh is accomplished by means of a CAS before RAS refresh cycle. The DRAM controller executes a refresh cycle when a refresh request is generated by the DRAM refresh counter. In the isolated memory area, refresh has the highest priority. If a CPU or DMA cycle is in progress when a refresh request is generated, the refresh controller will wait until the current cycle is finished. The refresh cycle will then be performed. If the CPU or DMA requests access to the isolated RAM while the refresh cycle is operating, it must wait until the refresh cycle is completed.

The isolated DRAM controller also provides access to the isolated DRAM by the MGC's DMA controller. CPU bus requests have priority over DMA controller bus requests.
G. DRAM Refresh Control 526

DRAM refresh generation logic 526 uses a CAS before RAS refresh cycle. The MGC DRAM refresh controller 526 consists of a counter that requests refresh cycles. The RAM must receive 1024 refresh cycles in no more than 16 milliseconds. The non-isolated and isolated DRAM controllers service the request by performing a refresh cycle. It is suggested that the refresh requests should be staggered so that isolated DRAM refresh cycles and non-isolated DRAM refresh cycles do not occur simultaneously.
H. MSP Bus Interface 503

The MSP bus interface 503 is driven by address multiplexer 518, control 519, and the MSP window register 520, to provide CPU and DMA access to up to 9 MSPs. The SIC decodes the 68340 address, control, and chip select signals, and generates the MSP address, chip enables and command strobes to the MSPs. The MSPs insert wait states into the bus cycle by asserting their MSP.sub.13 WAITL signals. The MGC terminates the 68340 bus cycle by asserting the DSACK1L signal after all the MSP WAITL signals go high, or after a specified number of clocks (16 MHZ) if no MSP.sub.13 WAITLs are asserted. The MGC supports only 16-bit accesses to the MSPs. Because the MSP data bus is isolated from the 68340 and peripheral buses, the CPU is able to access the non-isolated DRAM and peripherals during DMA transfers to/from the MSPs.

The CPU has higher priority when requesting bus access and can preempt DMA transfers to access the MSPs. The DMA.sub.13 CPUL signal is provided for easy transition between DMA and CPU accesses to the MSP internal areas.
I. MSP Windowing

The SIC windowing function provides simultaneous write access to multiple MSPs. For each MSP a corresponding bit in the CPU-MSP Window Register 520 or the DMA-MSP Window Register 520 determines if that MSP is to be accessed. When the CPU or DMA controller accesses the MSP "window area" the corresponding chip enable is asserted for each bit set in the CPU- or SMA-MSP window register 520.

A bus cycle to multiple MSPs is completed after all MSPs have completed the write, and release the wired-or MSP.sub.13 WAITL signals. The MSP "windo area" is write only. If a read access is attempted, all zeroes are returned.
J. Isolated DRAM-to-MSP DMA Controller 527

The SIC DMA control 527 supports DMA transfers between the 68340 Isolated DRAM 80 and the MSPs' DRAM and internal memory and register space. The MSP windowing function is also supported for multiple MSP write accesses. DMA reads from the MSP "window" (section H. above) are not supported, but DMA reads from a single MSP are. The DRAM and MSP address buses are separated, so that a complete DMA transfer only takes one bus cycle to complete. The DRAM read (write) and MSP write (read) occur simultaneously. The SIC DMA controller only supports 16-bit word transfers.

DMA transfer operation is determined by the DMA controller Registers 513 as defined below. Before starting a DMA transfer, the CPU must initialize the DRAM Address Register, MSP Address Register, Word Transfer Count Register, the DMA Control Register, and the appropriate pointer registers in the MSP. The DMA transfer is started by setting the ST bit in the DMA Control Register. DMA requests are generated internally whenever the word transfer count is greater than zero. No external requests are required or supported. The cycle length is extended by the MSP.sub.13 WAITL input to the SIC. When the DMA transfer is complete (word transfer count equals zero), the SIC clears the ST bit in the DMA Control Register and sets the DTC bit in the SIC Interrupt Status Register, and if enabled, asserts the SIC.sub.-- IRQL signal to the 68340. This interrupt is software maskable by the SIC Interrupt Enable Register.

The DMA controller 527 can be programmed to perform auto-increment or constant-address movements. The DRAM address can increment or remain constant, and the MSP address can increment or remain constant. During DMA transfers, the flow of data can be preempted for CPU access or refresh. The refresh has highest priority. That is, if a refresh cycle is requested, it will begin first, and the DMA and/or CPU will be made to wait until it is finished. The next lower level or priority is given to the CPU. That is, if the CPU is requesting access to the isolated DRAM or an MSP, the next available (no refresh) bus cycle will be given to it in preference over any DMA accesses being requested.
K. Peripheral Support

The Peripheral Bus Control 521 provides chip select and read and write strobes for the peripheral devices that operate on the CPU bus.
L. Clock Generation 522

The clock generation logic 512 generates 16 MHz, 8 MHz, 4 MHz, and 500 KHz square-wave clock outputs from a 32 MHz oscillator input. The SIC provides the 68340 CPU and TC8569AF (R) Floppy Disk controller with a 16 MHz clock input. The 8 MHz clock is provided for the keyboard processor in the user interface module and the SCSI controller, and the 4 MHz clock is provided for the LCD controller. The SIC also provides a 500 KHz clock output for the 68340 serial clock input to generate the MIDI clock. All clocks are generated synchronously to avoid system problems with clock skew between the various peripherals receiving them.
M. Serial Data Interface 511

The serial interface and registers 511 provide a four-wire serial data interface for communicating with the keyboard processor.
N. SIC Register Definitions
1. SIC Interrupt Status Register

The SIC Interrupt Status Register shown in FIGS. 5A provides the status for all MSPs, HSAB contention, serial interface and DMA interrupt sources. The bits of this register are masked by the SIC Interrupt Enable Register for generation of SIC.sub.-- IRQL signal to the 68340. If a bit in the SIC Interrupt Status Register is set, and the corresponding bit in the SIC Interrupt Enable Register is set, then the SIC.sub.-- IRQL output is asserted. The SIC Interrupt Enable Register does not mask the reading of this register. SI, CNT, and DTC are latched, and are cleared by a CPU read of this register. All Mn bits reflect the state of the MSP.sub.-- INTL(9 . . . 1) pins, and can only be cleared by clearing the Interrupt status registers in the MSPs. (Addr $00).
Mn-MSP #n Interrupt bit1=MSP #n interrupt was received.0=MSP #n interrupt was not received.SI-Serial Interface1=Serial Interface data transfer request was received.0=Serial Interface data transfer was not requested.CNT-HSAB Contention Error1=HSAB Contention detected.0=HSAB Contention not detected.DTC-DMA Transfer Complete1=DMA Transfer completed successfully.0=DMA Transfer not completed.Each of the interrupt sources has the same priority. Any of the enabled sources will generate an interrupt.
2. SIC Interrupt Enable Mask Register 525

The SIC Interrupt Enable Register shown in FIG. 5B selects the corresponding bits in the SIC Interrupt Status Register that cause an interrupt (SIC.sub.-- IRQL) to the CPU. If one of the bits in the SIC Interrupt Status Register is set, and the corresponding bit in the SIC Interrupt Register is set, then the SIC.sub.-- IRQL output is asserted. If a bit in the SIC Interrupt Enable Register is cleared, then the state of the corresponding bit in the SIC Interrupt Status Register does not effect the SIC.sub.-- IRQL output. (Addr $02).
Mn-MSP #n Interrupt Enable bit1=MSP #n interrupt enabled.0=MSP #n interrupt disabled.SI-Serial Interface Interrupt Enable bit1=Serial Interface interrupt enabled.0=Serial Interface interrupt disabled.DTC-DMA Transfer Complete Interrupt Enable bit1=DMA Transfer Complete interrupt enabled.0=DMA Transfer Complete interrupt disabled.
3. DMA Control Register 513

The DMA Controller Register shown in FIG. 5C determines the operation of the SIC's DMA controller. (Addr $04:).
DAI-DRAM Address Increment/Constant Bits1=The DRAM Address Register is incremented by 2 after 16-bit word transfer.0=The DRAM Address Register is not incremented after a transfer. The DRAM address that is written into the DMA DRAM Address Register is used for the complete DMA transfer.MAI-MSP Address Increment/Constant Bit1=the MSP Address Register is incremented by 2 after each 16-bit word transfer.0=The MSP Address Register is not incremented during operand transfer. The address that is written into the DMA MSP Address Register is used for the complete data transfer.
4. DMA MSP Address Register

The DMA MSP Address Register as shown in FIG. 5D contains the address of the MSP operand used by the DMA to access the MSP areas. The 16-bit address specified is the offset from the MSP space base address ($780000). This register can be programmed to increment or remain constant after each operand transfer. (Addr #06).
5. DMA DRAM Address Registers

The DMA DRAM Address Registers shown in FIGS. 5E and 5F contain the 23-bit address of the DRAM operand used by the DMA to access the isolated DRAM. These two 16-bit registers can be programmed to increment (by two) or remain constant after each operand transfer. (Addr $08 and Addr $0A). Address bit A[0] is not needed since it is always 0, and since the valid address range for DMA DRAM addresses is $60 0000 to $6F FFFF, address bits A[20 . . . 22] are always binary 110, and are also not needed. The unneeded bits should be hardwired internally to their fixed values as indicated in FIGS. 5E and 5F.
6. DMA Word Transfer Count Registers

The DMA Word Transfer Count Registers shown in FIGS. 5G and 5H contain the 19-bit number of 16 bit words to transfer using DMA. This 32 bit register field is decremented by one after each word transfer. When the DMA Word Transfer Count register becomes zero, the DTC bit in the SIC Interrupt Status Register is set, and the transfer is considered "complete." If enabled, the SIC.sub.-- IRQL input to the 68340 is asserted. When read, this register contains the count for the next access. When the most significant word is read (address $0C), the least significant word (address $0E) is latched. (Addr $0C and Addr $0E).
7. CPU-MSP Window Register 520

The CPU-MSP Window Register shown in FIG. 51 determines the MSPs accessed when the CPU accesses the MSP "windo area". (Addr #10).
Mn-Select MSP #n bit1=MSP #n selected.0=MSP #n not selected.
8. DMA-MSP Window Register 520

The DMA-MSP window register shown in FIG. 5J determines the MSPs accessed when the DMA controller accesses the MSP "window." (Addr #12).
Mn-Select MSP #n bit1=MSP #n selected.0=MSP #n not selected.
9. Serial Data Register 511

The Serial Data register shown in FIG. 5K stores the data received and transmitted on the serial interface. D<0> are the data bits. (Addr $14).
IV. The Music Signal Processor (MSP) (FIGS. 6 and 6A-6E)

FIG. 6 illustrates a functional block diagram of the music signal processor MSP. FIGS. 6A through 6E illustrate respective functional aspects of the MSP.

The MSP as shown in FIG. 6 operates in a host programmed environment, with multiple MSPs performing multitimbral music synthesis. The MSP contains specialized interfaces, including a host interface 200 a local RAM interface 201, and a high speed audio bus HSAB interface 202.

The host interface block 200 supports access to all internal areas of the MSP chip, that is the host can read and/or write all internal configuration, status and data registers transparent to the MSP's operation. The MSP also contains a conditional interrupt and LED interface 203 which includes at least two interrupt registers identifying which of a set of 32 possible interrupts require processing.

The RAM interface 201 supports dynamic RAM of up to 16 mega words of 24 bits. The high speed audio bus interface 202 provides 128 channels of transparent data flow among the MSPs, and allow algorithms to be spread across multiple MSPs for higher processing power.

The system includes two basic internal buses, including the X bus 204 and the Y bus 205. The primary processing resources include a 24.times.24 bit multiplier merged with a 56 bit accumulator (MAC 206), and an arithmetic logic unit ALU 207. The MAC 206 and ALU 207 share input latches, shifters, limiters and multiplexers which provide the inputs to the processing resources as described in more detail below.

The chip also includes two internal memory arrays referred to as the X memory 208 and the Y memory 209. Each the X memory 208 and Y memory 209 are 256 words of 24 bits each consisting of single port static RAMs. The X memory bank is a linearly indexed register array, while the Y memory bank includes segments using linear or circular addressing schemes.

The high speed audio bus interface 202 includes a register array of 64 words of 24 bits each implemented with static RAM. The host programs the mapping registers in the highspeed audio bus interface 202 to indicate which of the 128 times lots the local MSP will utilize on the high speed audio bus 202.

The system also includes an index register 210 which provides for indirect addressing into the X and Y memory spaces and into the RAM space provided the RAM interface 201.

Other components of the MSP includes a noise generator 211 which is coupled to the X bus 204 and the Y bus 205, and S/T register 212 also coupled to the X bus 204 and Y bus 205.

A microcode store 213 which is readable and writable by the host, and a prefetch buffer 214 coupled to the microcode store 213 and to the host CPU interface 200 are included. General chip clock and timing control 215 are integrated on the chip.

The data paths for MAC 206 and ALU 207 include an X input register 216 coupled to the X bus and a Y input register 217 coupled to the Y bus. The output of the X input register 216 and Y input register 217 are supplied to respective shifter/limiters 218, 219. The outputs of the shifter/limiters 218, 219 are supplied as inputs to 5 to 1 multiplexers 220 and 221 respectively. The other inputs to the 5 to 1 multiplexers include the value in the S register 212, the value in the T register 212, the output of the ALU 207, the output of the MAC 206. The MAC signal at the input of multiplexer 220 is supplied through shifter limiter 240. The ALU signal at the input of multiplexer 221 is supplied through shifter limiter 241. The outputs of the 5 to 1 multiplexers 220 and 221 are supplied into MAC input latches 222 and 223 respectively and directly as inputs the ALU 207. The output of the MAC input latches 222 and 223 are supplied into the MAC 206. The output of the MAC 206 is supplied to latch 224. The output of latch 224 is supplied to shifter 225 which is fed back through selector 226 to the MAC 206. The lower bits of latch 224 supplied to rounder 227. The output of the rounder 227 is coupled to the X and Y buses 204, 205, and to a comparator 228. Inputs to the comparator also include the values in the S and T registers 212.

The ALU 207, in addition to receiving the output of multiplexers 220 and 221, receives the value of the S register 212, the T register 212 and the index 210 as inputs. The ALU 207 generates an index output on line 229, and logic output on line 230, and a control output on line 231. The logic output on line 230 is supplied to latch 232, which drives the X bus on line 233 and the Y bus on line 234. The value on the X ALU output bus 233 is also supplied to the comparator 228.

The output of the comparator 228, control output on line 235 from the MAC 206, and the control output on line 231 from the ALU 207 are also supplied to the conditional interrupt and LED interface 203.

The X bus 204 and Y bus 205 carry operands among the data storage and processing blocks within the MSP. The buses are logically continuous, but there are pass transistors isolating some of the I/O functions from the main register bank, ALU, MAC buses.
A. Internal Timing Allocation

Timing of the MSP and the system it operates in are derived from the sample rate of the audio outputs. The MSP is intended to operate in a system operating a 48 KHz sampling rate, providing 512 microcode steps per system cycle. Each instruction cycle can include one register access on each of the X and Y buses and either a MAC or ALU operation. The ALU and MAC are separate, and can operate on independent data. They share the X and Y buses and the input multiplexers, so that only one MAC or ALU operation may be started per instruction cycle. The microcode must coordinate data movement among the register blocks, the HSAB, RAM, etc.

The microcode decode (not shown) includes a normal decode and special decode. The normal decode allows one register access on each of the X and Y buses to occur simultaneously with an ALU 207 or MAC 206 operation in one instruction cycle. The special decodes include the CONDITIONAL INTERRUPT and LED opcodes for interface 203. When a special decode instruction is executed, register accesses may not occur during the same instruction cycle because the input select field and the address fields are used for decoding the special decode instructions.

The ALU 207 can perform one calculation per instruction, and the MAC 206 can perform one calculation every two instruction cycles. Since the ALU 207 and MAC 208 both can receive inputs from themselves or each other, it is not always necessary to write the results into a register or RAM. In fact, write-back requires a separate instruction to be performed. Those instructions that result in an idle X or y bus can be utilized by Host Accesses through interface 200.
B. Clock and Timing

The clock and timing block 215 is responsible for generating the current microcode address, and updating it according to the current operational mode. The MSP can be halted, single stepped or allowed to free run. The Host can start the MSP at any time, but execution does not actually begin until the next synchronization pulse is received through the HSAB interface.

The MSP can be halted and single-stepped through software or hardware. There is a bit in the configuration register that controls that the run/halt state of the MSP, and there is a pin on the MSP package that also controls this. When the external signal is low, the MSP will be halted regardless of the register bit. When the external signal is high, the MSP will begin running after the register bit is set to one. When the external signal is high, if the register bit is cleared, the MSP will be halted. The register bit is reset (0) after hardware reset. Once the external signal and the register bit are both high, the MSP will begin execution on the first SYNC pulse received. When the MSP is halted, it continues to operate the high speed audio bus interface 202 and the CPU can read and write registers or the Ram areas memory interface 200.

When the MSP is halted by either internal or external means, the single step pin and register bit allow it to single-step for debugging purposes. A rising edge on the external step pin will cause the MSP to move one instruction further. This will only occur at the appropriate time. For instance, if the MSP is halted, pending execution of instruction number 95 when it receives a single-step command, it will wait until the time in the cycle that normally would have executed the step number 95. That single instruction will then be executed. After execution, the single step register bit will be reset to zero.

The CPU (FIG. 2) under normal operating (running) conditions must access the RAM area and internal X- and Y-buses in competition with the MSP. Since RAM access occur over more than one MSP instruction time, and internal cycles occur in less time than one CPU cycle, the MSP must be able to determine when there is sufficient time for the CPU to perform its access. To accomplish this, the MSP has a six-instruction prefetch queue 214. To fill this queue the CPU must allow at least 20 microseconds between when it loads the microcode at location zero and when it sets the run/halt bit. This will allow the MSP to fill its prefetch queue with the new instructions, and be ready to begin execution on the next SYNC pulse. This is also the case during single-stepping.

The program counter (PC) of the MSP is a synchronous 9-bit counter. There are actually two counters (one 9 bits, one 8 bits). The main (9 bit)) counter indicates which microcode step is actually executing. This is used for single-step triggering, and other functions which must know the exact instruction number. The second (8 bit) counter generates the addresses required for the microcode RAM to be read into the prefetch queue.

When the MSP is halted, the MSP does not perform any X or Y bus accesses, so the CPU can access the MSP's internal registers without wait-states. Before the Host sets the RUN/HALT bit, or single-steps the MSP, all host accesses should be completed i.e., if a host DMA RAM access is started, and the MSP's RUN/HALT bit is set before the access is completed, the results of the MSP's operation and the DMA operation are indeterminate.
C. Host CPU Interface

The host interface 200 allows the host processor to read and/or modify the internal registers of the MSP, and control its operation and configuration. It is the primary interface for setting the interrupt and control registers, as well using the RAM port 201, the HSAB port, and all the internal MSP registers. T
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The Host interface 200 must contend for the X and Y buses 204, 205 with the ALU 207 and other internal blocks. For this reason, the host interface 208 inserts wait states into a CPU cycle until the desired action can be accomplished. For example, a write to the X register area 208 that begins while the ALU 207 is using that area will generate host wait states until the write by the host can be accomplished.

The host does not have to poll a `ready` bit, and the bus arbitration inside the MSP is done transparent to the Host CPU access, allowing faster and simpler access to internal data. The control and configuration registers don't generate wait states to the host, nor do several other conditions of reading and writing. With this method of wait state generation, it is possible to write to multiple MSPs with the same CPU bus cycle. This is done by wire-or'ing the wait state signals together, and generating simultaneous chip select signals. This is actually a function of the system integration.

FIG. 6A illustrates the MSP windowing scheme which allows writing the multiple MSPs in parallel. Thus, FIG. 6A shows the host CPU 50, coupled to the system integration chip 73. System integration chip 73 receives chip select and address signals across lines 52/53, and receives control signals from the system integration chip 73 including the acknowledge signals 54. The system integration chip 73 drives a plurality of chips select signals 300-0 through 300-N to respective MSPs, MSP 150-0 through MSP 150-N.

The MSPs generate CPU wait states on active low line 301 having a passive pull-up 302. Also, the CPU supplies the read, write, and data strobe signals in parallel on active low line 303. This configuration causes transfers of data to the MSP data bus to be loaded in parallel to all MSPs having asserted chip select signals.

The CPU interface appears to the CPU as a 16-bit space of addresses, 2K words long. This entire space is not used, but the mapping allocates the full 2K. The Host interface block 200 performs all the packing and unpacking of MSP-sized words (16, 24, 56 and 80 bits) into one or more 16 bit words for the CPU to access. The data is latched internally when read or written. This allows the CPU to encounter to wait state only for the first word read, or the last word written in an access. The host CPU interface also performs all of the access decoding within the MSP for access to internal registers and ports.

The BIGENDIAN input pin determines the operation of the host-word to MSP-word data packing/unpacking. When this pin is a logic 1, the MSP registers are mapped as in a Big-Endian architecture, i.e., the lower addressed word of a double word is the most significant word. When this pin is a logic 0, the MSP registers are mapped as in a Little-Endian architecture, i.e., the lower addressed word of a double word is the least significant word.

The main components required to accomplished the host interface 200 include:
Host Read/write portHost-Word to MSP-Word data packing/unpackingHost Address decodingHost Wait State GeneratorHost write- and read-through control & timing
D. Conditional & Interrupt Interface 203

There is always a need to alert the host processor that some condition requires its attention, and there is always a need for conditional execution of program code. The MSP provides both through interrupts and execution flags. Execution flags are further divided into normal if-then-else operation, and a special no-op function most often used when downloading microcode blocks.

The MSP chip is designed to provide up to 32 sources of interrupts to the host CPU. These can be generated by any of the 512 MSP instructions. The Host CPU is alerted to an interrupt when any of the non-masked interrupts are triggered. This occurs when an INT (#, <condition>) instruction is executed, if the condition indicated is true, the interrupt bit # specified is set. If this bit is not masked, the interrupt signal is set low. The host then reads the interrupt request registers to determine which of them require processing. When an interrupt request registers to determine which of them require processing. When an interrupt request register is read by the CPU, all the triggered interrupts in that register are cleared. An interrupt (#, <condition>) instruction, where the condition is one of the latched bits (ALU LATCHED OVERFLOW, MAC CLIPPED), also clears the corresponded latched bit. The host can mask any of the interrupts writing to the interrupt mask registers. All interrupts can be disabled and cleared by writing a "1" to the corresponding bit in the interrupt request registers. At reset, all interrupts are masked.

The MSP also provides a method for conditional code execution. There are two execution flags in the MSP: the if-then-else flag, and the no-op flag. The flags' states can be either true or false. The if-then-else flag's state is affected by three sources. When code is operating in the MSP, if this flag is set false, all instructions to be executed while the flag is false are prevented from writing any results back to RAM or any other destination. This continues until something resets the if-then-else flag. This allows the MSP to maintain synchronization with the rest of the system while providing conditional code execution.

The if-then-else flag can be set by the state of conditions within the ALU or MAC. FIG. 6B illustrates the operation the if-then-else flag. The figure schematically illustrates the MSP microcode 310. A segment of the MSP Code 311 includes a sequence of instructions 312 through 318. The execution flag value at the end of each instruction takes the state indicated in column 319 if the condition is true, and takes the state indicated in column 320 if the condition is false. "C" code for instructions 313 through 317 is provided on the outside of the column 320 for reference.

The MSP code 311 includes a first operation in line 312. For this operation, the state of the execution flag will be true independent of any conditions. For a conditional routine, which is illustrated in the C code "if <condition> then", the first instruction is provided on line 313 which sets the execution flag on satisfaction of the condition. Thus, if the condition is true, as indicated in column 319, the execution flag will remain true. If the condition is false as indicated in column 320, the execution flag will be reset false. This results an execution of the condition met code 314 if the condition was true, or no execution of the condition met code if the condition was false as indicated in column 320. At the end of the condition met code 314, an invert flag instruction is provided on line 315. This results in resetting the execution flag to false if the condition were true, and setting the execution flag to true if the condition were false as indicated in columns 319 and 320. This results in no execution of the condition not met code 316 if the condition were true, and execution of the condition not met code 316 if the condition were false. At the end of the condition not met code 316, a set flag true instruction if provided on line 317. This results in setting the execution flag true for the subsequent code 318 independent of conditions.

FIG. 6B also provides a table of conditions supported using the execution flag. The chip also includes an external condition input pin as one of the conditions supported. Thus, a microcode instruction may test the input signal of the external condition bit, and operate the if-then-else flag on the condition being true.

The second flag, the no-op flag, is set when the host programs the NOP count register to a non-zero value. This is used during microcode download, and causes the indicated number of instructions to be ignored, regardless of their effect on any flags. There is no opcode to reset the no-op flag. The intent is that when a portion of microcode is being replaced, the CPU initializes the NOP start and NOP count registers and then writes the microcode block. The CPU then resets the no-op flag by writing zero to the NOP count register. This provides a simple and safe method for code downloading while the MSP is still operating.

The main pieces that make up block 203 are:
Conditional State control & storageNOP instruction counter, NOP start, NOP count registersData Read & Writeback controlInterrupt Mask/Request Registers.Interrupt Request Signal generator
E. High Speed Audio Bus (HSAB) Interface

The MSP is equipped with facilities in the HSAB interface 202 to communicate between other MSPs, so that signal synthesis and processing can be accomplished on more than one chip. This is a high speed serial-parallel audio data bus (HSAB). The bus carries 128 independent channels of 24-bit audio information. Each channel can be assigned to one or more MSPs by host programming. Data is passed along the bus from a transmitter to all receivers in two 12-bit half-words. The DAAD chip 154 (FIG. 4) is the bus master for this bus, and provides timing and synchronization for it and the MSP as a whole.

FIG. 6C provides a schematic block diagram of the HSAB interface 202. The interface includes a 24 bit wide multiplexer 330 coupled to the X-bus 204, Y bus 205, and a 64 word buffer RAM 331. The multiplexer 330 receives data from the X bus 204, Y bus 205, or the HSAB data RAM for supply to the HSAB control block 332. This block drives HSAB data on line 340, and generates HSAB control signals such as the clock and sync signals on lines 341 and 342 respectively. Also, data received from the bus is driven as input to the multiplexer 330 for supply to any one of the X bus 204, Y bus 204, or HSAB data RAM 331. Control of multiplexer 330 is supplied by timing line 333 from the control and timing block 332. This also controls a multiplexer 334 which supplies address information to the data buffer RAM 331. A bus mapping RAM 335 is provided which is used to map up to 64 of the available 128 channels on the HSAB to the local MSP. Addresses for the mapping RAM 335 are supplied by multiplexer 336 at the output of a map address counter 337, which is controlled by the control timing block 332. A second input to multiplexer 336 is the host address. The mapping registers 335 provide read and write address information to the multiplexer 334, with a write address latch 338 providing write timing.

The multiplexer 334 receives addresses from the mapping registers 335, the host address, the X-address or the Y-address which is provided from the instruction decode.

The MSP HSAB map RAM 335 provides fully programmable I/O channel-to-HSAB data RAM mapping. Because there are 64 words of data buffer RAM 331, each MSP is capable of using up to 64 channels of I/O. The map RAM 335 indicates which of the channels receive data from the bus, and which of the channels transmit data from the local MSP onto the bus. By configuring the map registers 335 in plurality of MSPs, point to point communication on the HSAB is defined. This provides for writing into MSP accessible register space in each of the MSPs in the array, or to the audio output structure as necessary for particular voice programs being executed.

The MSP provides the ability to use up to 64 HSAB channels in each chip. The MSP contains a RAM space 331 of 64 Words.times.24 Bits for HSAB data. The HSAB MAP RAM 335 allows the host to program which channels are to be transmitted on, received from, or not used at all by this MSP. In the map RAM, for each of the 128 I/O channels, there is a usage enable bit U, a direction bit D and a 6-bit address which maps the 10 channel to one of the 64 locations in the SAAB data RAM.

In normal operation, only one MSP or DAAD 154 will be enabled for transmitting on any given channel. However, during system integration and debug, there is a possibility that two or more MSPs may be programmed to transmit at the same time. The DAAD 54 provides contention detection logic which is used to prevent multiple MSPs from driving the HSAB simultaneously. Each MSP asserts its HSABOEL signal on I/O slot prior to when it will transmit. The DAAD receives the HSABOEL signal from each MSP and DAAD, and if two or more HSABOEL signals are asserted at the same time, the HSABCNTERRL signal is asserted. The MSPs then disable transmitting on the HSAB during the next I/O time slot.

The HSAB data RAM 331 is a single-port RAM. There are therefore some software restrictions which must be placed on its access. An HSAB channel word is transmitted across the bus every four MSP microcode instructions. At the end of the second half-word's transmission (when enabled), the next HSAB data word must be read. During the first part of the first half-word's transmission for the next channel, the received data from the previous channel's time slot must be written to the data RAM. These activities require that two of the four MSP microcode cycles be reserved for this use. The MSP microcode compiler must understand and obey this requirement, and not attempt to access the HSAB data RAM during these instruction times. Should this happen, the error bit, HSAB ACCESS ERROR will be set and latched in the CPU status register.

The HSAB is enabled/disabled by the HSAB.sub.-- ENABLE bit in the MSP Configuration register. After RESET, the HSAB is disabled. When the host has programmed the configuration and map registers, it sets the HSAB.sub.-- ENABLE bit to "1". The MSP waits for the next synchronization mechanism. After power-on reset, all MSPs are in the halted state. A synchronization signal is sent by the DAAD chip at the 48 KHz system rate after the end of the RESET signal. When the host has programmed all the internal registers, microcode, RAM, and configuration registers, etc., it sets all the MSPs to the run mode. The MSPs each wait for the next synchronization signal from the I/O control block. This pulse causes the MSPs to reset their internal microcode pointer to the first instruction and begin operation. This insures that the MSPs are always in synchronization, even in single step mode.

The major functions included in the High Speed Audio Bus Interface 202 are:
HSAB Data RAMHSAB MAP RAMHSAB MAP CounterHSAB timing & control generator
F. RAM Interface

The MSP's RAM interface 201 provides access to a large area of memory. The MSP provides 24 bits of address range or 16 MW.times.24 bits. The physical RAM space is broken into eight areas by the DRAM RAS signals. The address bus is folded in half to support dynamic RAM.

The writable RAM space is allocated into two parts, in which the addressing methods are different. The first area is addressed circularly, and is used for delay lines. The second area allows standard linear and table-lookup space for samples, envelope tables, etc. These two addressing methods are depicted in FIGS. 6D and 6E, respectively. The tables and delay line definitions are set with 64 dual-use configuration register set 350, shown in FIGS. 6D and 6E.

FIG. 6D logically illustrates the mapping of the delay line/table memory coupled to MSP. It includes a delay line area 349 and table space 350. The delay line area is limited by the range of the decrementing position counter in the RAM interface indicated as DLTOP 351. There are up to 64 logical delay line positions 0 through 63, and a number of table spaces 352.

The difference between the offset for slot 6 and the offset for slot 5 defines the number of samples in delay line 5. In the example, this difference may be 2000. If the delay line 5 is limited to 2000 samples long, and only 900 have been written, those samples delayed beyond 900 cycles are invalid. In the case that 900 have been written since the last reset, the count length in the delay line 5 will be equal to 900. The write address for the delay line is calculated by adding the offset for the selected delay line number to the value of the decrementing position counter (Modulo DLTOP).

A read address for the delay line, if the delay line is less than or equal to the count length in the register file 350 for the delay line, is equal to the value of the decrementing position counter plus the offset plus the delay for the sample to be read (Modulo DLTOP). A table address for a given table number and index from MSP bus is equal to the DLTOP value plus the offset for the table in the register file 350 plus the index.

The logic for generating the address is shown in FIG. 6E. The inputs include a partition base value 370 from the register file, a decrement counter reset signal 371 and a cycle start signal 372 from the MSP. Also, a delay line/table index signal 374 is supplied. A decrement counter 373 receives reset signal 371 and the cycle start signal 372. The partition base value and decrement counter outputs are supplied to a multiplexer 375. The output of the multiplexer 375 provides a base address on line 376 in response to the DL/T bit in register file 350. Offset values can be provided from the table offset or delay line length from the index register 377 in the MSP 77 across line 378. Also, the offset value from the register file 350 is supplied on line 379. The values on lines 378 and 379 are added by adder 380 to supply an offset value on line 381. The base value in line 376 and offset value in line 381 are added by adder 382. The output of the adder 382 is used directly as a table address, and supplied to modulo logic 383 which receives the DLTOP reference on line 384. The output of the modulo logic 383 as supplied as the delay line address on line 385. Multiplexer 386 controlled by the DL/T bit in the register file 350 supplies the memory access address to register 387. An even/odd half word select bit 388 is supplied from the host.

Each delay line/table configuration entry consists of three parts: a base offset, a count, and a bit DL/T indicating whether the record is a delay line or table. The base offset always indicates the start of the particular delay line or table. The count's use depends upon the setting of the DL/T bit. When the DL/T bit is set for tables, the count register of the configuration entry does nothing, and has no effect on accesses. When this bit is set for a delay line, the count is used to gate data on delay line reads. After a delay line has been initialized by setting this count to zero, each write to the delay line increments the counter. When a read of the delay line is requested, if the delay line length requested is longer than the number of samples actually stored since the count was initialized, the value zero will be returned for the read. If the delay line length is less that the count, the actual data stored in memory will be returned. The count stops when it reaches $FFFF, after which any delay line length will be accepted, and the data value at the address will be provided. This allows delay lines to be initialized without having to actually fill memory with zeroes.

In a delay line, writing usually occurs at the head of the delay line, and reading usually occurs on some sample stored earlier. For writing, the address is composed of the partition base value, the offset value for that delay line, and the output of a decrement counter. The decrement counter moves all the delay lines through the circular addressing area as system cycles pass. When reading, the delay line length from the index register is added to the decrement counter and base offset for that delay line to get the desired address.

The CPU, under normal operating (running) conditions must access the RAM area in competition with the MSP's accesses. Since RAM accesses occur over more than one MSP instruction time, the MSP must be able to determine if there will be sufficient time for the CPU to perform its access. To accomplish this, the MSP has a six-instruction prefetch queue.

The CPU downloads data to RAM at a single-word register in the MSP register map. The address where downloaded data is written to (or read from) by the CPU is determined by the settings of the two RAM pointers. One pointer is used when the CPU accesses the RAM port directly. The second is used when the system integration chip is performing a DMA transfer. Which of these are used is determined by the setting of the CPUDMAL input signal's value at the start of the access.

The functional blocks required to implement the RAM control block 201 are:
RAM Address Folding MultiplexerRAM access address latchesRAM access data latchesRAS, CAS, WE timing generatorsRAM configuration registersRAM circular/linear split registerCircular addressing counterRAM address calculatorRAM Data Packing / Unpacking logic
G. Pseudo Random Noise Generator

The pseudo random noise generator 211 provides 24 bit numbers to either the X or the Y Internal data bus. The noise generator output is defined as: N.sub.n =5*N.sub.n-1 +1. A filtered noise generator output is also provided and defined as: FN.sub.n =(N.sub.n +N.sub.n-1)/2. The noise register is clocked each time a read as indicated by RD ACCESS is performed by the MSP or CPU. The Host CPU can read the pseudo random noise generator through the X- or Y-bus to provide it with a pseudo random noise generator. The CPU can also seed the random number generator by writing to it. The noise and filtered noise registers are mapped at the top of the HSAB data memory.
H. Microcode Storage Block & Prefetch Block

The microcode storage block 213 and prefetch block 214 are implanted with a single-port static RAM with separate I/Os. There are 512 microcode steps of 40 bits each, stored as 256 words of 80 bits. The microcode contains information about the current operation. This is prefetched three full words (six instructions) ahead, so the MSP can determine when an internal bus phase, or RAM are access will be available for the host CPU.

The CPU downloads microcode in full 80 bit blocks, which require five 16 bit word writes to assemble. The location where the assembled word is placed is determined by the setting of the appropriate microcode pointer register. There are two such pointers. One is used when the system integration chip DMA logic is downloading microcode, and the other is used when the CPU is accessing the microcode port directly. Which pointer is used is determined by the state of the CPUDMAL input signal at the start of the access. The microcode is stored in two instruction words to allow the CPU access to the memory block while the MSP is operating. With this method, there is always time reserved for new microcode to be downloaded.

Microcode can be downloaded in a forward direction only. The MSP supports microcode download while the MSP is both halted and running. The NOP start and NOP count registers are used when a portion of the microcode needs to be modified, and it is desired that the MSP remain operating while that code segment is replaced.
I. X & Y Register Storage Blocks

The X & Y register blocks 208, 209 consist of two banks of static RAM registers providing internal data storage for fast access to the MAC and ALU. The X register bank 208 can be accessed from the X internal bus only, and the Y register bank 209 can be accessed from the Y internal bus only. Each bank is 256 Words.times.24 bits wide. The CPU can access these register banks, but it may require one or more wait states to accomplish the access due to internal instruction executions.

The Y register bank is divided into two spaces at the point defined by the Y Circular/Linear Split Point Register. This register contains a 3-bit value which specifies the number of words of circular memory: 0, 4, 8, 16, 32, 65, 128, or 256. The lower part is addressed circularly, the upper part is addressed linearly. An 8-bit decrement counter, decremented every system cycle, moves data through the circular addressing area. The circular address is composed of the output of the decrement counter, the microcode address field and , if an indirect addressing mode is used, the contents of the index register. The linear address is composed of the microcode address field and the contents of the index register (if an indirect address mode is used). Circular or linear addressing is determined by the microcode address field. If the microcode address is less than the circular/linear split point, then circular addressing is used; otherwise linear addressing is used.
J. Temporary Registers S and T

There are two temporary registers 212, each a 24 bit register, used as temporary storage of data values. These can be accessed from either the X or the Y internal bus, or can be selected by the multiplexers at the inputs to the MAC and ALU. The registers are referred to as the T and the S registers. The data stored in the temporary registers is also output to the compare block 228 at the output of the MAC and ALU.
K. 24 Bit.times.24 Bit Multiplier & 56 Bit Accumulator

The MAC 206 is the most time-critical part of the MSP. The speed of the multiplier determines the minimum instruction time. A multiply and accumulate in less that the 80 ns worst case should satisfy a 25 MIPs throughput goal. This block consists of a 24 bit.times.24 bit high speed fixed point multiplier. The final partial-product adder has been merged with the 56-bit accumulator. It can perform signed (2s complement) multiplies in single precision, and can handle the bit shifting required for double precision multiplies. It can also invert the sign on the Y input if programmed. The X- and Y-Inputs come from the X- and Y-bus latches and multiplexers described below.

Inputs to the MAC are latched as they are accessed to insure correct results, since the multiply cycle takes two full instruction times. The MAC output is 56 total bits in width, but only the 24-bit rounded result can be written back on the X- or Y-bus. The accumulator result generates several flags for the conditional interface and status registers. The 24-bit rounded result is also fed to the compare block. The second input to the 56 bit accumulator can be either the zero value, the currently accumulated (latched) value, or the accumulated value shifted 23 bits for double precision multiplies.

Because the microcode and multiplier do not support unsigned or mixed-mode multiples, the MSB of the LSW of a double precision number is used as a sign bit and must always be zero. Therefore, the MSPs double precision multiplies are actually 24 bit.times.47 bit or 47 bit.times.47 bit.

The MAC operations execute in two 40 ns instruction cycles, and may include one register access on each of the X- and Y-buses. The MAC can perform the following operations:
______________________________________ NOP no operation SMPY Signed Multiply SMPYMINUS Signed Multiply, Y-Input Inverted SMAC Signed Multiply/Accumulate SMACMINUS Signed Multiply/Accumulate, Y-input Inverted SMACSHIFT23 Signed Multiply/Accumulate, double precision SMACMINUSSHIFT23 Signed Multiply/Accumulate, double precision, Y-input inverted ______________________________________

The functional blocks required for the multiplier and accumulator include the following:
24 Bit.times.24 bit=48 bit result signed partial-product multiplier56 Bit accumulator (merged with the multiplier)Output multiplexer and write-back latch
L. 24 Bit ALU

The ALU 207 block provides non-standard Arithmetic-Logic-Unit functions from the MSP. It performs on a 40 ns cycle time, and can provide write-back to both the X and Y register areas. The two inputs to the ALU come from separate multiplexers. The ALU result generates several flags for the conditional interface and status registers. The output of the ALU is fed to the compare block and the X- and Y-bus write back latches. There are two latches here because the value in the accumulator might be used to generate two parts of the same number, for example a whole number and fractional portion of a phase increment value.

The ALU operations execute in one 40 ns instruction cycle, and may include one register access on each of the X- and Y-buses. The ALU can perform the following operations:
______________________________________ NOP no operation SADD Signed addition UADD Unsigned addition SSUB Signed subtraction (X - Y) USUB Unsigned subtraction (X - Y) SADDABS Signed addition (X + .vertline.Y.vertline.) SSUBABS Signed subtraction (X - .vertline.Y.vertline.) NEGATE Negate input value (2s complement) ABS Absolute value SIGN Sign extract ENVELOPE Calculate envelope value, delta, destination and segment table control, etc. OSCILLATOR1 Calculate phase angle and interpolation constant OSCILLATOR2 Calculate phase angle and interpolation constant. HAMMER Calculate phase angle and interpolation constant SAMPLE Calculate phase angle and perform loop control (16-bit integer, 8-bit fraction) SAMPLE1 Calculate phase angle and perform loop control (24-bit fraction) SAMPLE2 Calculate phase angle and perform loop control (24-bit integer) INTERPOLATE Calculate 1 - x COPY Copy operand source to accumulator X,Y ASR1 Arithmetic shift right 1 bit ASL1 Arithmetic shift left 1 bit ASR4 Arithmetic shift right 4 bits ASL4 Arithmetic shift left 4 bits DITHER Randomizes least significant bit(s) for output to DAC ONEMINUSABS Calculate 1 - .vertline.x.vertline. LIMITPOSITIVE Limit negative numbers to zero ______________________________________
M. Special Decode Instructions

The special decode operations execute in one 40 ns instruction cycle. During a special decode instruction cycle, register accesses on the X- and Y-buses are not allowed. The special decode instructions include the following operations:
______________________________________ INT #, <condition> Interrupt the CPU with vector bit # if <condition> is true SET FLAG, <condition> set conditional flag if <condition> is true LED, <condition> turn on LED if <condition> is true ______________________________________
N. Compare block

The compare block 228 detects when the data output of the ALU or MAC meets several conditions. These include "less that T or S (temporary register)", "greater that T or S (temporary register)", and "almost equal T or S (temporary register)". ("almost equal T or S" is defined as equal to zero within a threshold specified by T or S.)
0. Rounder

The rounder 227 uses a convergent rounding technique to round the output of the MAC to fit the 56 bit result into the 24 bit MSP word size. It also performs limiting on numbers exceeding the MAC's range. Convergent rounding is a variation of the "standard" rounding technique. Standard rounding consists of adding the constant 0.times.800000 to the 56-bit MAC result. When using a twos-complement data representation, this method introduces a positive bias in the roundoff error. Convergent rounding attempts to eliminate this bias. Convergent rounding initially performs standard rounding and then the result is tested to determine if bits 0-23 are zero, If this condition is true, bit 24 is cleared. The result is that if the MAC output is exactly half way between two numbers, then the result will be rounded up half the time and rounded down the rest of the time. Therefore the roundoff error averages to zero.
P. Index register

The MSP contains one index register 210 allowing indirect addressing to the four main data storage areas. The index register can be written by either the X or the Y internal bus and can be read and set by the Host processor. The Index register is 24 bits in width and can be incremented automatically.
Q. Input Registers

There are two registers, 216, 217 used to latch the X- and Y-bus data before being used as inputs to the ALU of MAC.
R. Input Shifters/Limiters

There are four shifter/limiters 218, 219, 240, 241, used to shift/limit the ALU/MAC X and Y input operands. The MAC, ALU, X- or Y-input register data is shifted/limited according to the current microcode word. For signed operations, the shifter performs an arithmetic shift, and for unsigned operations, a logical shift is performed. The signed/unsigned status also determines the limit value to be used.
S. Input Multiplexers

There are two multiplexers 220, 221, one on each of the ALU/MAC X and Y inputs, those connected to the X-inputs select data from the MAC, ALU, T, S, or X-input register. Those connected to the Y-inputs select data from the MAC, ALU, T, S, or Y-input register. The MAC, ALU<X- and Y-input register data may also be shifted/limited as defined by the microcode.
T. MSP Register Description

This section discusses the register definitions appearing at the MSP Host interface 200. They include the internal data spaces, status registers, configuration registers, RAM and microcode ports and pointers, etc.
1. X- and Y-Registers

The X- and Y- register areas 208, 209 are first in the register map. They are memory mapped; accessed directly without the benefit of an MSP internal pointer. These registers must be accessed over the internal X- and Y-buses, so wait states may be generated to the CPU before the access can be accomplished. Wait states are not inserted on the second word read to a continuing internal word, nor to the first of two writes. The words in these areas are all 24-bits wide, so they are presented to the 16-bit host interface as two 16 bit words. For BIGENDIAN=1, the LSbit of the higher addressed word is the LSbit of the MSP's word. For BIGENDIAN=0, the LSbit of the lower addressed word is the LSbit of the MSP's word. There are 256 24-bit words in each bank, so the 2 banks occupy a total of 2048 bytes of address space.
2. HSAB Data & Map Registers

These registers are in the HSAB interfaces 202 are in two adjacent address spaces within the MSP. The lower addressed one is the high speed audio bus data memory. This internal memory is 64 words.times.24 bits wide. These registers must be accessed over the internal X- and Y-buses, so wait states may be generated to the CPU before the access can be accomplished. Wait states are not inserted on the second word read to a continuing internal word, nor to the first of two writes. The words in these areas are all 24-bits wide, so they are presented to the 16-bit host interface as two 16 bit words. For BIGENDIAN=1, the LSbit of the higher addressed word is the LSbit of the MSP's word. For BIGENDIAN=0, the LSbit of the lower addressed word is the LSbit of the MSP's word. There are 64 24-bit words, which occupies a total of 256 bytes of address space. The HSAB data RAM can be read and written by the CPU.

The second part of this block is the HSAB map registers. Each sixteen bit register contains the configuration bits for two HSAB channels. For each channel there are 8 bits: a usage enable bit, a direction bit, and a 6-bit address bit which maps the I/O channel to one of the 64 locations in the HSAB data RAM. The USE bit, when set to one, indicates that the MSP uses this channel. When set to zero, the MSP does not use that channel, and the state of the other bits are meaningless (don't care). The DIRECTION bit indicates, when set to zero, that this MSP is to receive data on this channel. When set to one, it indicates that data will be transmitted on this channel by this MSP. There are sixty-four 16 bit registers, for a total of 128 bytes of CPU address space. Because the HSAB controller must access the map registers during operation, wait states may be generated to the CPU before the access can be completed. They are all read/writable.
3. Delay Line/Table Position Registers

These registers provide the MSP with flexible tables and delay lines. The MSP supports any combination of delay lines and table, up to 64 in number. There are two areas in these registers. The first defines the table/delay line base offset, and whether that entry is a table or a delay line. The second part is the count of accumulated samples for that delay line. None of these registers generates wait states.

The first area, the delay line offset values, consists of sixty four 24 bit values. They are presented to the 16-bit host interface as two 16 bit words each. For BIGENDIAN=1, the LSbit of the lower addressed word is the LSbit of the MSP's word. The bit number 8 of the MSW tells the MSP RAM address calculation unit whether this entry is a delay line (1) or a table (O). When defined as a delay line, the value represents the offset from the moving head of delay line memory that is the writing point for that delay line. When defined as a table, the value represents the offset from the RAM partition value that is the start of the table. This area is sixty four 25 (24+1) bit words long, which occupies a total of 256 bytes of address space.

The second area consists of 64 16 bit registers. When the table entry is set as a delay line, this value represents the number of data values written since this register was set to zero by the CPU. This allows the MSP to emulate having had its delay lines cleared without taking the time to actually fill the RAM with data. The counter is incremented upon the delay line's site. During a delay line read, the length requested is compared to this value to determine if the stored value should be provided, or if a zero value should be returned. This counter will saturate at FFFF, so don't count on having a gated delay line of greater than 64K. When the table entry is set as a table, the count register is unused.

These registers do not produce wait-states to the CPU, and all can be read and written.
4. MSP Functional Registers

These registers control the configuration, operation, and status of the MSP chip. Some in this group of registers do not produce any waitstates to the processor, while others do. Some cannot be written, some cannot be read. Here are brief descriptions of each:
a. RAM Data Port

This is the register through which the CPU accesses the MSP's RAM area. As noted in the section previously covering the RAM interface block, the first read, and the second write to this port produces wait states until the operation is accomplished. This single-address register is in fact two registers, accessed according to the state of the CPUDMAL signal at the start of the access. To access memory through this port, the DMA or CPU RAM Start Address register must be programmed with the start address.
b. Microcode Data Port

This is the register through which microcode is downloaded. Because the microcode prefetch controller must access the microcode RAM during operation, wait states may be generated to the CPU before the access can be completed. This single-address register is in fact two registers, accessed according to the state of the CPUDMAL signal at the start of the access. Each microcode word requires five word accesses to complete. Downloading through this part requires that the DMA or CPU microcode start address register be programmed with the desired start address.
c. RAM Start Pointer (DMA)

This register sets the start point for DMA accesses to the MSP RAM. This register contains the 24-bit RAM address, and is automatically incremented as accesses progress. This register is read/write. When reading, this register contains the current 24-bit RAM address. This register affects only DMA accesses, and produces no wait states to the CPU.
d. RAM start pointer (CPU)

This register sets the start point for CPU accesses to the MSP RAM. This register contains the 24-bit RAM address, and is automatically incremented as accesses progress. This register is read/write. When reading, this register contains the current 24-bit RAM address. This register affects only direct CPU accesses, and produces no wait states to the CPU.
e. Microcode Start (DMA)

This register sets the start point for microcode accesses in the MSP. This register holds the 8-bit address of a double-instruction microcode word, and is automatically incremented as accesses progress. This register is write only. This register affects only DMA accesses, and produces no wait states to the CPU.
f. Microcode Start (CPU)

This register sets the start point for microcode accesses in the MSP, and also indicates the current microcode step number if read while single stepping. This register holds the 8-bit address of a double-instruction microcode word, and is automatically incremented as accesses progress. This register can be read and written. When read, this register contains the current 9-bit microcode step number. This register affects only direct CPU accesses, and produces no wait states to the CPU.
g. MAC Output

This register is the 56-bit result of the Multiplier-Accumulator. This value is presented to the CPU in four sixteen bit registers. They are read/writable, but only when the MSP is halted. These registers do not produce wait states to the CPU. When writing, the value in the registers is placed into the MAC output register when the last word is written; write them all in order.
h. ALU Output Register X

This register is the 24-bit result of the ALU, and is the value currently in the X bus writeback register. It is read and writable, but only when the MSP is halted. These registers do not produce any wait states to the CPU. When writing, the value is placed in the internal register when the word with the highest address is written. This register is 24-bits wide, and appears to the 16-bit host interface as a long word. For BIGENDIAN=1 the LSbit of the higher addressed word is the LSbit of the MSP's word. For BIGENDIAN=0, the LSbit of the lower addressed word is the LSbit of the MSP's word.
i. ALU Output Register Y

This register is the 24-bit result of the ALU, and is the value currently in the Y bus writeback register. It is read and writable, but only when the MSP is halted. These registers to do not produce any wait states to the CPU. When writing, the value is placed in the internal register when the word with the highest address is written. This register is 24-bits wide, and appears to the 16-bit host interface as a long word. For BIGENDIAN=1, the LSbit of the higher addressed word is the LSbit of the MSP's word. For BIGENDIAN=0, the LS bit of the lower addressed word is the LSbit of the MSP's word.
j. Temporary Register T

This register is the 24 bit value currently in the T temporary register. It is read and writable, but only when the MSP is halted. This register must be accessed over the internal X- and Y buses, so wait states may be generated to the CPU before the access can be accomplished, though this is generally not a problem when single-stepping the MSP. Wait states are not inserted on the second word read to a continuing internal word, nor to the first of two writes. When writing, the value in the registers is placed into the internal register when the word with the highest address is written. This register is 24-bits wide, so it is presented to the 1-bit host interface as a long word. For BIGENDIAN=1, the LSbit of the higher addressed word is the LSbit of the MSP's word. For BIGENDIAN=0, the LSbit of the lower addressed word is the LS bit of the MSP's word.
k. Temporary Register S

This register is the 24-bit value currently in the S temporary register. It is read and writable, but only when the MSP is halted. This register must be accessed over the Internal X- and Y-buses, so wait states may be generated to the CPU before the access can be accomplished, though this is generally not a problem when single-stepping the MSP. Wait states are not inserted on the second word read to a continuing internal word, nor to the first of two writes. When writing, the value in the registers is placed into the internal register when the word with the highest address is written. This register is 24-bits wide, so it is presented other 16-bit host interface as a long word. For BIGENDIAN=1, the LSbit of the higher addressed word is the LSbit of the MSP's word. For BIGENDIAN=0, the LS bit of the lower addressed word is the LSbit of the MSP's word.
l. Noise Register

This register is the 24-bit value currently in the pseudo-random noise generator register. It is read and writable. This register must be accessed over the internal X- or Y-bus, so wait states may be generated to the CPU before the access can be accomplished. This is generally not a problem, since the MSP is usually halted when the random number generators are seeded. Wait states are not inserted on the second word read to a continuing Internal word, nor to the first of two writes. When writing, the value in the registers is placed into the internal register when the word with the highest address is written. This register is 24-bits wide, so it is presented to the 16-bit host interface as a long word. For BIGENDIAN-1, the LSbit of the higher addressed word is the LSbit of the MSP's word. For BIGENDIAN=0, the LSbit of the lower addressed word is the LSbit of the MSP's word. The noise generator is cycled when the CPU reads from it as well as when the MSP reads it.
m. Filtered Noise Register

This register is the 24-bit value currently in the filtered noise register. It is read only. This register must be accessed over the internal X- or Y-bus, so wait states may be generated to the CPU before the access can be accomplished. Wait states are not inserted on the second word read to a continuing internal word. This register is 24-bits wide, so it is presented to the 16-bit host interface as a long word. For BIGENDIAN=1, the LSbit of the higher addressed word is the LSbit of the MSP's word. For BIGENDIAN=0, the LSbit of the lower addressed word is the LSbit of the MSP's word.
n. Index Register

This register is the 24-bit value currently in the index register. It is read and writable, but only when the MSP is halted. This register must be accessed over the internal X- and Y-buses, so wait states may be generated to the CPU before the access can be accomplished, though this is generally not a problem when single-stepping the MSP. Wait states are not inserted on the second word read to a continuing internal word, nor to the first of two writes. When writing, the value in the register is placed into the internal register when the word with the highest address is written. This register is 24-bits wide, so it is presented to the 16-bit host interfaces as a long word. For BIGENDIAN=1, the LSbit of the higher addressed word is the LSbit of the MSP's word. For BIGENDIAN=0, the LSbit of the lower addressed word is the LSbit of the MSP's word.
o. Interrupt Mask Register

This register is a 16-bit read/write register. Each bit represents which interrupt sources should be masked (O) from creating a CPU interrupt. Interrupt numbers 0-15 appear in this register. This register does not produce any wait states to the CPU. At RESET, all interrupts are masked.
p. Interrupt Mask Register 2

This register is a 16-bit read/write register. Each bit represents which Interrupt sources should be masked (O) from creating a CPU interrupt. Interrupt numbers 16-31 appear in this register. This register does not produce any wait states to the CPU, at RESET, all Interrupts are masked.
q. Interrupt Request Register 1

This register is a 16-bit read/write register. Each bit represents one Interrupt source in the MSP. When read, those Interrupt bit positions which generated an Interrupt will be high. When this register is read, all the bits are cleared. The Interrupt request bits can be cleared individually by writing a "1" to the corresponding bit in the Interrupt request registers. Interrupt numbers 0-15 appear in this register. This register does not produce any wait states to the CPU. At RESET, all Interrupts are cleared.
r. Interrupt Request Register 2

This register is a 16-bit read/write register. Each bit represents one Interrupt source in the MSP. When read, those Interrupt bit positions which generated an Interrupt will be high. When this register is read, all the bits are cleared. The Interrupt request bits can be cleared individually by writing a "1" to the corresponding bit in the Interrupt request registers. Interrupt numbers 16-31 appear in this register. This register does not produce any wait states to the CPU. At RESET, all Interrupts are cleared.
s. DRAM Circular/Linear Split Point Register

This 24-bit register indicates to the MSP where the delay line memory ends, and the table space begins. The spilt point register value contains the last location in memory used for Delay lines. This value must fit with the 2N-1 form, so it forms a mask of the bits allowable in the address. This register does not produce any wait states to the CPU. When writing, the value in the registers is placed into the Internal register when the word with the highest address is written. This register is 24-bits wide, so it is presented to the 16-bit host Interface as a long word. For BIGENDIAN=1, the LSbit of the higher addressed word is the LSbit of the MSP's word. For BIGENDIAN=0, the LSbit of the lower addressed word is the LSbit of the MSP's word. This register is read/write.
t. Y Circular/Linear Split Point Register

Any comments?
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cello
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PostPosted: Fri Oct 25, 2013 9:09 am    Post subject: Reply with quote

Yes.

Please stop.
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Jedi Simon
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PostPosted: Fri Oct 25, 2013 9:10 am    Post subject: Reply with quote

Overflow problems?
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michelkeijzers
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PostPosted: Fri Oct 25, 2013 9:45 am    Post subject: Reply with quote

FIG. 6E is a logic diagram of the RAM addressing block of the MSP.

FIG. 7 provides memory and hardware model of the dynamic voice allocation system according the present invention.

FIG. 8 is an overview block diagram of the voice allocation processing sequence according to the present invention.



This fragment above is from your post ... I dont' see figures, can you add them?
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Kontrol49
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PostPosted: Fri Oct 25, 2013 3:56 pm    Post subject: Reply with quote

cello wrote:
Yes.

Please stop.


I've not bothered to read Jedis threads,life's too short.....but boy they are great for testing how fast your iPad can scroll to the bottom of the page...

I got here in 4 seconds Mr. Green
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Bald Eagle
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PostPosted: Fri Oct 25, 2013 5:10 pm    Post subject: Reply with quote

Kontrol49 wrote:


I've not bothered to read Jedis threads,life's too short.....but boy they are great for testing how fast your iPad can scroll to the bottom of the page...

I got here in 4 seconds Mr. Green

lol ... This thread really does test your scrolling skills if nothing else.
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